公开(公告)号：US3925804A

公开(公告)日：1975-12-09

申请号：US43765074

申请日：1974-01-29

Applicant: WESTINGHOUSE ELECTRIC CORP

Inventor： CRICCHI JAMES RONALD ,  RUEHLING BARRY W

IPC: G11C16/04 ,  H01L21/8246 ,  H01L23/29 ,  H01L29/792 ,  H01L29/78 ,  H01L29/34

CPC classification number: H01L27/11568 ,  G11C16/0466 ,  H01L23/29 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/3011 ,  H01L2924/00

Abstract: The structure of and the method of processing is disclosed for providing a MNOS element comprised of diverse regions within a semiconductive member. A first silicon oxide layer is disposed to cover a first portion of the semiconductive substrate, other than that in which the MNOS element is formed. A second silicon oxide layer is disposed to cover a second portion of the semiconductive member in which the MNOS element is formed. A conductive element is connected to one of the MNOS regions and overlies the first portion of the member. A first layer of a nitride such as Si3N4 is deposited at a rate in the range of 40 to 60 A/minute to cover the silicon oxide layer, whereby a nitride-oxide interface charge of a magnitude and polarity is established to inhibit the formation of a parasitic region within the semiconductive member, due to the application of a voltage signal to the conductive element. In a further aspect, either or both memory and non-memory MNOS elements may be fabricated in a manner to include drain and source regions spaced from each other with its second silicon oxide layer covering the channel formed therebetween, and a gate electrode disposed thereon. In the formation of a memory MNOS element, the second oxide layer covering the second portion of the member is reduced, e.g. by etching, to a thickness in the order of 7 to 9 A. Next, in the fabrication of both memory and non-memory MNOS elements, a second nitride layer is deposited at a rate in the order of 75 to 150 A, whereby the nitride-oxide interface charge is minimized. A plurality of such memory MNOS elements may be formed into a matrix, wherein the row and column conductors are insulated from each other. The deposition of the first nitride layer at the rate specified above inhibits the formation of parasitic regions beneath the row and column conductors. Further, memory and non-memory MNOS elements may be fabricated upon a common semiconductive substrate by simplified fabrication techniques. In particular, the second deposition of silicon nitride is carried out at a rate in the order of 100 A/minute, whereby a minimum nitride-oxide interface charge is established to ensure the effective operation of the non-memory MNOS element and to increase the memory hysteresis window of the memory MNOS element.

Abstract translation: 公开了结构和处理方法，用于提供由半导体构件内的不同区域组成的MNOS元件。 第一氧化硅层设置成覆盖半导体衬底的第一部分，而不是形成MNOS元件的第一氧化硅层。 第二氧化硅层设置成覆盖形成有MNOS元件的半导体部件的第二部分。 导电元件连接到MNOS区域中的一个并且覆盖在构件的第一部分上。 以40〜60A /分钟的速度沉积氮化物如Si 3 N 4的第一层以覆盖氧化硅层，从而建立大小和极性的氮氧化物 - 界面电荷以抑制形成 由于向导电元件施加电压信号，半导体元件内的寄生区域。

公开(公告)号：US3588526A

公开(公告)日：1971-06-28

申请号：US3588526D

申请日：1969-04-04

Applicant: WESTINGHOUSE ELECTRIC CORP

Inventor： CRICCHI JAMES RONALD

IPC: G11C19/28 ,  G11C19/18 ,  G11C19/00

CPC classification number: G11C19/184

Abstract: A TWO-STAGE SHIFT REGISTER CIRCUIT FOR AN N BIT SHIFT REGISTER COMPRISED OF A METAL OXIDE SILICON TRANSISTOR (MOST) ARRAY OF A SINGLE-TYPE SEMICONDUCTIVITY WHEREIN EACH STAGE INCLUDES A LOAD MOST AND A SWITCHING MOST AND WHEREIN A SEPARATE GATING MOST IS COUPLED TO EACH LOAD AND SWITCHING MOST OF BOTH STAGES AND OPERATED FROM A FOUR-PHASE SYNCHRONIZED CLOCK SOURCE SO THAT THE LOAD AND SWITCHING MOST IN EACH STAGE ARE OPERATED IN PUSH-PULL RELATIONSHIP FOR REDUCING THE POWER DRAWN DURING STATIC CONDITIONS AND REDUCING THE PROPAGATION TIME FROM THE INPUT AND OUTPUT OF EACH BIT.

公开(公告)号：US3895360A

公开(公告)日：1975-07-15

申请号：US43764974

申请日：1974-01-29

Applicant: WESTINGHOUSE ELECTRIC CORP

Inventor： CRICCHI JAMES RONALD ,  BLAHA FRANKLYN C

IPC: G11C17/00 ,  G11C7/00 ,  G11C8/04 ,  G11C16/02 ,  G11C16/04 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  H03K19/177 ,  G11C11/40

CPC classification number: G11C16/0466 ,  G11C8/04

Abstract: A block oriented random access memory (BORAM) is disclosed as comprising a plurality of memory arrays of metal-nitride-oxide semiconductor (MNOS) memory elements. Each memory array includes a plurality of the MNOS memory elements disposed in rows and columns, and serial or sequential means such as a shift register for writing and reading data to and from the memory elements through column conductors associated with each column of the memory elements. A temporary storage means such as a latch is inserted between each stage of the shift register and the column conductor, whereby a multiplexing function can be performed between the stage outputs of the shift register and the columns of the memory elements. Address means is provided for the rows of memory elements, whereby a row may be selected for entry of data through its associated column conductor. In one illustrative embodiment, a plurality of such assemblies is assembled into a block capable of being separately addressed, wherein each such assembly is capable of storing one bit of a multi-bit word of data. In turn, a plurality of such blocks is assembled to form the block oriented random access memory, wherein each such block may be randomly accessed, and the data therein sequentially read and written.

Abstract translation: 公开了一种面向块的随机存取存储器（BORAM），其包括多个金属 - 氮化物 - 氧化物半导体（MNOS）存储元件的存储器阵列。 每个存储器阵列包括以行和列布置的多个MNOS存储器元件，以及串行或顺序装置，例如移位寄存器，用于通过与存储器元件的每一列相关联的列导体向存储元件写入和读取数据。 诸如锁存器的临时存储装置被插入在移位寄存器的每一级和列导体之间，由此可以在移位寄存器的级输出和存储元件的列之间执行复用功能。 为存储器元件行提供地址装置，由此可以选择一行用于通过其相关联的列导体输入数据。 在一个说明性实施例中，多个这样的组件被组装成能够被单独寻址的块，其中每个这样的组件能够存储一位多位数据字。 反过来，多个这样的块被组合以形成面向块的随机存取存储器，其中每个这样的块可以被随机存取，并且其中的数据顺序地被读取和写入。

公开(公告)号：US3588527A

公开(公告)日：1971-06-28

申请号：US3588527D

申请日：1969-04-04

Applicant: WESTINGHOUSE ELECTRIC CORP

Inventor： CRICCHI JAMES RONALD

IPC: G11C19/28 ,  H03K19/096 ,  G11C19/00

CPC classification number: G11C19/28

Abstract: AN N-BIT SHIFT REGISTER WHEREIN EACH BIT IS COMPRISED OF COMPLEMENTARY PAIRS OF INDUCED CHANNEL FIELD EFFECT TRANSISTORS FABRICATED UPON A SEMICONDUCTOR SUBSTRATE AND BEING DOPED TO COMPRISE BOTH ENHANCEMENT MODE P-CHANNEL AND DEPLETION MODE N-CHANNEL DEVICES BY PREDETERMINED DOPING SURFACE CONCENTRATION FOR OBTAINING FASTER OPERATION TIME BUT EFFECTIVELY OPERATING THE DEPLETION MODE DEVICES AS ENHANCEMENT MODE DEVICES BY MEANS OF APPLYING A PREDETERMINED BIAS POTENTIAL TO THE SUBSTRATE. BY SELECTIVE GROUPING OF THE COMPLEMENTARY PAIRS OF FIELD EFFECT TRANSISTORS THE OPERATION MAY BE ACCOMPLISHED BY AS LITTLE AS A SINGLE-CLOCK SIGNAL.