公开(公告)号：US20230359573A1

公开(公告)日：2023-11-09

申请号：US18347642

申请日：2023-07-06

申请人： WUXI ESIONTECH CO., LTD.

发明人： Yueer SHAN ,  Yanfeng XU ,  Jicong FAN ,  Tong LIU ,  Hua YAN

IPC分类号： G06F13/20 ,  G06F12/0802

CPC分类号： G06F13/20 ,  G06F12/0802 ,  G06F2213/40 ,  G06F2212/60

摘要： An FPGA for implementing data transmission by using a built-in edge module is provided. The FPGA is provided with a built-in edge module. A read port of each resource module connected to the edge module in the FPGA is separately connected to a winding architecture and the edge module, and/or a write port of each resource module connected to the edge module in the FPGA is separately connected to the winding architecture and the edge module. The edge module includes a read/write controller and a cache unit. The read/write controller simultaneously reads data from read ports of a plurality of resource modules and temporarily stores the read data in the cache unit. Alternatively, the read/write controller simultaneously writes temporarily stored data in the cache unit into write ports of the plurality of resource modules.

公开(公告)号：US20220328452A1

公开(公告)日：2022-10-13

申请号：US17311943

申请日：2020-12-30

申请人： WUXI ESIONTECH CO., LTD.

发明人： Jicong FAN ,  Yueer SHAN ,  Yanfeng XU ,  Yanfei ZHANG ,  Hua YAN

IPC分类号： H01L25/065 ,  H01L23/00 ,  H03K19/17736 ,  H01L23/538

摘要： A semiconductor device includes an active silicon connection layer therewithin to integrate a die. A power terminal of a die functional module within the die is connected to a connection point lead-out terminal through a silicon stack connection point. A power gating circuit is arranged within the silicon connection layer. A power output terminal of the power gating circuit within the silicon connection layer is connected to the corresponding connection point lead-out terminal of the die and thus connected to the power terminal of the die function module, so that the power gate circuit can control power supply to the die function module according to an obtained sleep control signal, and the idle die function module can enter into a sleep state to save power.

公开(公告)号：US20220216156A1

公开(公告)日：2022-07-07

申请号：US17294985

申请日：2020-12-30

申请人： WUXI ESIONTECH CO., LTD.

发明人： Jicong FAN ,  Yanfeng XU ,  Yueer SHAN ,  Hua YAN ,  Yanfei ZHANG

IPC分类号： H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L23/535

摘要： The present disclosure discloses an FPGA device forming a network-on-chip by using a silicon connection layer. An active silicon connection layer is designed inside the FPGA device. A silicon connection layer interconnection framework is arranged inside the silicon connection layer. Bare die functional modules inside an FPGA bare die are connected to the silicon connection layer interconnection framework to jointly form the network-on-chip. Each bare die functional module and a network interface and a router that are in the silicon connection layer interconnection framework form an NOC node. The NOC nodes intercommunicate with each other, so that the bare die functional modules in the FPGA bare die without a built-in NOC network can achieve efficient intercommunication by means of the silicon connection layer interconnection framework, reducing the processing difficulty on the basis of improving the data transmission bandwidth and performance inside the FPGA device.

公开(公告)号：US20230353161A1

公开(公告)日：2023-11-02

申请号：US18347660

申请日：2023-07-06

申请人： WUXI ESIONTECH CO., LTD.

发明人： Zhengzhou CAO ,  Feige XIA ,  Yueer SHAN ,  Hua YAN

IPC分类号： H03M1/00 ,  H03M1/12

CPC分类号： H03M1/002 ,  H03M1/1255

摘要： A chip state monitoring circuit based on a self-balancing differential signal integration and amplification circuit is provided. The chip state monitoring circuit is built in a chip, and can sense a state signal of the chip and transmit the state signal to a chip configuration circuit after performing amplification and analog-to-digital conversion, such that the chip configuration circuit can monitor a state and provide a timely feedback or response, thereby improving reliability and a service life of the chip. The chip state monitoring circuit uses a brand new self-balancing differential signal integration and amplification circuit. With a built-in positive coefficient integration network and negative coefficient balancing network, the self-balancing differential signal integration and amplification circuit can perform amplification by required times to enter a self-balancing stable state, thereby achieving fixed-multiple amplification without timed reading. The control method is simple and flexible.

公开(公告)号：US20220344268A1

公开(公告)日：2022-10-27

申请号：US17421460

申请日：2020-12-30

申请人： WUXI ESIONTECH CO., LTD.

发明人： Yueer SHAN ,  Yanfeng XU ,  Jicong FAN ,  Yanfei ZHANG ,  Hua YAN

IPC分类号： H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H03K19/17796 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1776 ,  H03K19/17764

摘要： The present application discloses a multi-die FPGA implementing a built-in analog circuit using an active silicon connection layer, and relates to the field of FPGA technology. The multi-die FPGA allows multiple small-scale and small-area dies to cascade to achieve large-scale and large-area FPGA products, reducing processing difficulties and improving chip production yields. Meanwhile, due to the existence of the active silicon connection layer, some circuit structures that are difficult to implement within the die and/or occupy a large die area and/or have a low processing requirement can be laid out in the silicon connection layer, solving the existing problems of making these circuit structures directly within the die. Part of the circuit structures can be implemented within the silicon connection layer and the rest in the die, which helps optimize the performance of FPGA products, improve system stability, and reduce system area.

公开(公告)号：US20220006733A1

公开(公告)日：2022-01-06

申请号：US17236400

申请日：2021-04-21

申请人： WUXI ESIONTECH CO., LTD.

发明人： Yanfeng XU ,  Yueer SHAN ,  Jicong FAN ,  Yanfei ZHANG ,  Hua YAN

IPC分类号： H04L12/775 ,  H04L12/933

摘要： The present disclosure discloses an FPGA device for implementing a network-on-chip transmission bandwidth expansion function, and relates to the technical field of FPGAs. When a predefined functional module with built-in hardcore IP nodes is integrated in an FPGA bare die, soft-core IP nodes are configured and formed by using logical resource modules in the FPGA bare die and are connected to the hardcore IP nodes to form an NOC network structure, so as to increase nodes and expand the transmission bandwidth of the predefined functional module. On the other hand, the soft-core IP nodes can be additionally connected to input and output signals in the predefined functional module and also can expand the transmission bandwidth of the predefined functional module.