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1.发明公开公开(公告)号：US20230385222A1
公开(公告)日：2023-11-30
申请号：US18446501
申请日：2023-08-09
发明人： Xiaojie MA , Yanfeng XU , Yuting XU , Boyin CHEN , Yanfei ZHANG , Yueer SHAN
CPC分类号： G06F13/4068 , G06F11/27
摘要： A high-speed low-latency interconnect interface (HLII) for silicon interposer interconnection is provided. The HLII is configured to perform large-scale input/output (I/O) interconnection on a silicon interposer, and includes a physical link (PL) and an LL (LL). The LL receives a data signal, a configuration signal, and a control signal of logical resource inside a chiplet, and can complete data conversion, parity check, training, channel repair, instruction stream generation, and other functions for the PL. The PL receives and transmits a data signal converted by the LL. The PL includes a high-speed I/O port, a first input first output (FIFO), and related control logic. The high-speed I/O port of the PL is compatible with both a double date rate (DDR) transmission mode and a single data rate (SDR) transmission mode.
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公开(公告)号：US20220114052A1
公开(公告)日：2022-04-14
申请号：US17645314
申请日：2021-12-21
发明人： Yueer SHAN , Yanfeng XU , Zhenkai JI , Feng HUI
IPC分类号： G06F11/10 , G01R31/3177
摘要： A field programmable gate array (FPGA) for improving the reliability of a key configuration bitstream by reusing a buffer memory includes a configuration buffer, a configuration memory and a control circuit. The configuration memory includes N configuration blocks. The FPGA stores a key configuration chain by using the configuration buffer and ensures correct content of the key configuration chain through an error correcting code (ECC) check function of the configuration buffer, so that when the FPGA runs normally, a control circuit reads the key configuration chain in the configuration buffer at an interval of a predetermined time and writes the key configuration chain into a corresponding configuration block to update the key configuration chain, thereby ensuring accuracy of the content of the key configuration chain and improving running reliability of the FPGA.
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3.发明公开公开(公告)号：US20230353500A1
公开(公告)日：2023-11-02
申请号：US18348385
申请日：2023-07-07
发明人： Yueer SHAN , Yanfeng XU , Jicong FAN , Zhenkai JI
IPC分类号： H04L47/625
CPC分类号： H04L47/625
摘要： A routing node scheduling method for an NOC in an FPGA is used when a plurality of input ports each have a data packet to be transmitted to a routing node at the same time. A scheduling controller within the routing node is used to enable each input port according to a predetermined scheduling order, and the routing node receives a data packet through the enabled input port. In addition, quantities of times at least two input ports are enabled are different in one scheduling cycle, which means that the scheduling controller implements biased scheduling control over each input port, allowing different input ports to transmit data packets at different frequencies. This can increase a quantity of times an input port with high communication importance is enabled, making a data packet at the input port be transmitted more timely and achieving better transmission efficiency. The scheduling method can well match transmission requirements of different services to achieve optimal transmission performance of an NOC.
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4.发明公开公开(公告)号：US20230367683A1
公开(公告)日：2023-11-16
申请号：US18346892
申请日：2023-07-05
发明人： Xiaojie MA , Xiaochen HU , Yanfeng XU , Yuting XU , Yanfei ZHANG , Yueer SHAN
CPC分类号： G06F11/27 , G06F13/4282
摘要： An apparatus and a method for testing a multi-channel high-speed low-latency interconnect interface (HLII) for a silicon interposer are provided. The apparatus includes: a standard test port configured to exchange a test instruction; an asynchronous bypass port configured to directly access an input/output (I/O) port of a channel of a physical layer of the interconnection interface; a built-in self-test (BIST) engine configured to implement inter-level loopback testing and data verification; a redundant data channel configured to repair a damaged data channel; and a delay chain testing circuit configured to test a function and linearity of a delay chain. The apparatus embeds test and repair logic into the physical layer and a link layer, achieving internal test control without any external controller. In this way, a sample can be tested and quickly screened to ensure its performance.
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5.发明公开公开(公告)号：US20230359573A1
公开(公告)日：2023-11-09
申请号：US18347642
申请日：2023-07-06
发明人： Yueer SHAN , Yanfeng XU , Jicong FAN , Tong LIU , Hua YAN
IPC分类号： G06F13/20 , G06F12/0802
CPC分类号： G06F13/20 , G06F12/0802 , G06F2213/40 , G06F2212/60
摘要： An FPGA for implementing data transmission by using a built-in edge module is provided. The FPGA is provided with a built-in edge module. A read port of each resource module connected to the edge module in the FPGA is separately connected to a winding architecture and the edge module, and/or a write port of each resource module connected to the edge module in the FPGA is separately connected to the winding architecture and the edge module. The edge module includes a read/write controller and a cache unit. The read/write controller simultaneously reads data from read ports of a plurality of resource modules and temporarily stores the read data in the cache unit. Alternatively, the read/write controller simultaneously writes temporarily stored data in the cache unit into write ports of the plurality of resource modules.
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公开(公告)号：US20230020524A1
公开(公告)日：2023-01-19
申请号：US17955578
申请日：2022-09-29
发明人： Yueer SHAN , Zhengzhou CAO , Wenhu XIE , Yanfei ZHANG , Ting JIANG , Bo TU
IPC分类号： H03K19/17748 , H03K19/20
摘要： A configuration circuit of a flash FPGA for realizing external monitoring and configuration is provided. In the configuration circuit, a positive high-voltage output terminal of a positive high-voltage charge pump is connected to a positive high-voltage external monitoring port through a positive high-voltage bidirectional switch circuit, and the positive high-voltage output terminal of a positive high-voltage charge pump is further configured as a positive output end of a voltage supply circuit. A negative high-voltage output terminal of a negative high-voltage charge pump is connected to a negative high-voltage external monitoring port through a negative high-voltage bidirectional switch circuit, and the negative high-voltage output terminal of a negative high-voltage charge pump is further configured as a negative output end of the voltage supply circuit. Based on a received mode adjustment signal, a mode control circuit controls to enter an external monitoring mode or an external configuration mode.
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公开(公告)号：US20220328452A1
公开(公告)日：2022-10-13
申请号：US17311943
申请日：2020-12-30
发明人： Jicong FAN , Yueer SHAN , Yanfeng XU , Yanfei ZHANG , Hua YAN
IPC分类号： H01L25/065 , H01L23/00 , H03K19/17736 , H01L23/538
摘要： A semiconductor device includes an active silicon connection layer therewithin to integrate a die. A power terminal of a die functional module within the die is connected to a connection point lead-out terminal through a silicon stack connection point. A power gating circuit is arranged within the silicon connection layer. A power output terminal of the power gating circuit within the silicon connection layer is connected to the corresponding connection point lead-out terminal of the die and thus connected to the power terminal of the die function module, so that the power gate circuit can control power supply to the die function module according to an obtained sleep control signal, and the idle die function module can enter into a sleep state to save power.
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公开(公告)号：US20230352096A1
公开(公告)日：2023-11-02
申请号：US18348380
申请日：2023-07-07
发明人： Zhengzhou CAO , Yueer SHAN , Bo TU , Xiaofei HE , Yanfei ZHANG , Zhenkai JI
IPC分类号： G11C16/10 , G11C16/04 , H03K19/017
CPC分类号： G11C16/102 , G11C16/0433 , H03K19/01721
摘要： A configuration control circuit of a flash-type FPGA capable of suppressing programming interference is provided. The configuration control circuit adds a programming selection circuit compared with a conventional configuration control circuit. When a programming operation is performed on a flash memory cell located in a target row and a target column, the programming selection circuit controls a path between a programming bit line (BL) voltage and a BL voltage obtaining terminal of the flash memory cell located in the target row and the target column to be turned on, and a path between the programming BL voltage and a BL voltage obtaining terminal of a flash memory cell located in another row and the target column to be turned off.
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公开(公告)号：US20220415422A1
公开(公告)日：2022-12-29
申请号：US17903061
申请日：2022-09-06
发明人： Zhengzhou CAO , Yueer SHAN , Yanfei ZHANG , Yan JIANG , Yuting XU , Hui XU
摘要： In an anti-fuse programming control circuit based on a master-slave charge pump structure, a master charge pump module obtains an external voltage and is connected to a plurality of slave charge pump modules. Each slave charge pump module is connected to an anti-fuse bank. The distance between the layout position of each slave charge pump module and the layout position of the connected anti-fuse bank does not exceed a predetermined distance. Based on a programming voltage output by each slave charge pump module to the connected anti-fuse bank, the feedback network outputs a feedback signal corresponding to the slave charge pump module to the master charge pump module. Based on the feedback signal corresponding to each slave charge pump module, the master charge pump module adjusts a master drive signal provided to the slave charge pump module to stabilize the programming voltage output by the slave charge pump module.
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公开(公告)号：US20220216156A1
公开(公告)日：2022-07-07
申请号：US17294985
申请日：2020-12-30
发明人： Jicong FAN , Yanfeng XU , Yueer SHAN , Hua YAN , Yanfei ZHANG
IPC分类号： H01L23/538 , H01L25/065 , H01L23/00 , H01L23/535
摘要： The present disclosure discloses an FPGA device forming a network-on-chip by using a silicon connection layer. An active silicon connection layer is designed inside the FPGA device. A silicon connection layer interconnection framework is arranged inside the silicon connection layer. Bare die functional modules inside an FPGA bare die are connected to the silicon connection layer interconnection framework to jointly form the network-on-chip. Each bare die functional module and a network interface and a router that are in the silicon connection layer interconnection framework form an NOC node. The NOC nodes intercommunicate with each other, so that the bare die functional modules in the FPGA bare die without a built-in NOC network can achieve efficient intercommunication by means of the silicon connection layer interconnection framework, reducing the processing difficulty on the basis of improving the data transmission bandwidth and performance inside the FPGA device.
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