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公开(公告)号：US20090058703A1
公开(公告)日：2009-03-05
申请号：US11846916
申请日：2007-08-29
IPC分类号： H03M1/66
CPC分类号： H03M1/745 , H01L29/7855
摘要： A digital to analog converter. The digital to analog converter including a current mirror comprising N stages, each stage comprising 2n−1 dual gate transistors where N is a positive integer equal to or greater than one and n is an integer between 0 and N−1 for each of the N-stages, values of n being different for each stage of the N stages; an output, every dual gate transistor of each stage of the N stages connected to the output; N inputs, every input of the N inputs connected to a different stage of the N stages, any particular input of the N inputs connected to every dual gate transistor of a stage to which the particular input is connected to; and a current reference circuit, comprising a reference current source and a reference dual gate transistor, each stage of the N stages connected to the current reference circuit.
摘要翻译： 数模转换器。 数模转换器包括电流镜，包括N级，每级包括2n-1个双栅极晶体管，其中N是等于或大于1的正整数，并且对于N中的每一个，n是0和N-1之间的整数 阶段，n阶段的每个阶段的值不同; 一个输出，N级每级的每个双栅极晶体管连接到输出端; N个输入，N个输入的每个输入连接到N级的不同级，N个输入的任何特定输入连接到特定输入连接到的级的每个双栅极晶体管; 以及电流参考电路，包括参考电流源和参考双栅极晶体管，N级的每一级连接到电流参考电路。
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公开(公告)号：US07545297B2
公开(公告)日：2009-06-09
申请号：US11846916
申请日：2007-08-29
IPC分类号： H03M1/00
CPC分类号： H03M1/745 , H01L29/7855
摘要： A digital to analog converter. The digital to analog converter including a current mirror comprising N stages, each stage comprising 2n−1 dual gate transistors where N is a positive integer equal to or greater than one and n is an integer between 0 and N−1 for each of the N-stages, values of n being different for each stage of the N stages; an output, every dual gate transistor of each stage of the N stages connected to the output; N inputs, every input of the N inputs connected to a different stage of the N stages, any particular input of the N inputs connected to every dual gate transistor of a stage to which the particular input is connected to; and a current reference circuit, comprising a reference current source and a reference dual gate transistor, each stage of the N stages connected to the current reference circuit.
摘要翻译： 数模转换器。 数模转换器包括电流镜，包括N级，每级包括2n-1个双栅极晶体管，其中N是等于或大于1的正整数，并且对于N中的每一个，n是0和N-1之间的整数 阶段，n阶段的每个阶段的值不同; 一个输出，N级每级的每个双栅极晶体管连接到输出端; N个输入，N个输入的每个输入连接到N级的不同级，N个输入的任何特定输入连接到特定输入连接到的级的每个双栅极晶体管; 以及电流参考电路，包括参考电流源和参考双栅极晶体管，N级的每一级连接到电流参考电路。
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3.发明授权Design structure for a digital-to-analog converter using dual-gate transistors 失效使用双栅极晶体管的数模转换器的设计结构公开(公告)号：US07545298B2
公开(公告)日：2009-06-09
申请号：US12045055
申请日：2008-03-10
IPC分类号： H03M1/00
CPC分类号： H03M1/745 , H01L27/1203 , H01L29/785 , H01L29/7855 , H01L29/78648
摘要： A design structure embodied in a machine readable medium, the design structure including a current mirror including N stages, each stage comprising 2n−1 dual gate transistors where N is a positive integer equal to or greater than one and n is an integer between 0 and N−1 for each of the N-stages, values of n being different for each stage of the N stages; an output, every dual gate transistor of each stage of the N stages connected to the output; N inputs, every input of the N inputs connected to a different stage of the N stages, any particular input of the N inputs connected to every dual gate transistor of a stage to which the particular input is connected to; and a current reference circuit, comprising a reference current source and a reference dual gate transistor, each stage of the N stages connected to the current reference circuit.
摘要翻译： 体现在机器可读介质中的设计结构，该设计结构包括包括N级的电流镜，每级包括2n-1个双栅极晶体管，其中N是等于或大于1的正整数，n是0和 N-1，对于N级的每个阶段，n的值不同; 一个输出，N级每级的每个双栅极晶体管连接到输出端; N个输入，N个输入的每个输入连接到N级的不同级，N个输入的任何特定输入连接到特定输入连接到的级的每个双栅极晶体管; 以及电流参考电路，包括参考电流源和参考双栅极晶体管，N级的每一级连接到电流参考电路。
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4.发明申请DESIGN STRUCTURE FOR A DIGITAL-TO-ANALOG CONVERTER USING DUAL-GATE TRANSISTORS 失效使用双门极晶体管的数字到模拟转换器的设计结构公开(公告)号：US20090058704A1
公开(公告)日：2009-03-05
申请号：US12045055
申请日：2008-03-10
IPC分类号： H03M1/66
CPC分类号： H03M1/745 , H01L27/1203 , H01L29/785 , H01L29/7855 , H01L29/78648
摘要： A design structure embodied in a machine readable medium, the design structure including a current mirror including N stages, each stage comprising 2n-1 dual gate transistors where N is a positive integer equal to or greater than one and n is an integer between 0 and N−1 for each of the N-stages, values of n being different for each stage of the N stages; an output, every dual gate transistor of each stage of the N stages connected to the output; N inputs, every input of the N inputs connected to a different stage of the N stages, any particular input of the N inputs connected to every dual gate transistor of a stage to which the particular input is connected to; and a current reference circuit, comprising a reference current source and a reference dual gate transistor, each stage of the N stages connected to the current reference circuit.
摘要翻译： 体现在机器可读介质中的设计结构，该设计结构包括包括N级的电流镜，每级包括2n-1个双栅极晶体管，其中N是等于或大于1的正整数，n是0和 N-1，对于N级的每个阶段，n的值不同; 一个输出，N级每级的每个双栅极晶体管连接到输出端; N个输入，N个输入的每个输入连接到N级的不同级，N个输入的任何特定输入连接到特定输入连接到的级的每个双栅极晶体管; 以及电流参考电路，包括参考电流源和参考双栅极晶体管，N级的每一级连接到电流参考电路。
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5.发明申请公开(公告)号：US20090113357A1
公开(公告)日：2009-04-30
申请号：US11923784
申请日：2007-10-25
IPC分类号： G06F17/50
CPC分类号： H01L31/103 , G11C5/005 , G11C11/4125 , H01L31/115 , H01L31/118 , H03K19/0033
摘要： A method, device and system for monitoring ionizing radiation, and design structures for ionizing radiation monitoring devices. The method including: collecting an ionizing radiation induced charge collected by the depletion region of a diode formed in a silicon layer below an oxide layer buried below a surface of a silicon substrate; and coupling a cathode of the diode to a precharged node of a clocked logic circuit such that the ionizing radiation induced charge collected by a depletion region of the diode will discharge the precharged node and change an output state of the clocked logic circuit.
摘要翻译： 用于监测电离辐射的方法，装置和系统，以及用于电离辐射监测装置的设计结构。 该方法包括：收集由埋在硅衬底表面下方的氧化物层下面的硅层中形成的二极管的耗尽区收集的电离辐射感应电荷; 以及将二极管的阴极耦合到时钟逻辑电路的预充电节点，使得由二极管的耗尽区收集的电离辐射感应电荷将放电预充电节点并改变时钟逻辑电路的输出状态。
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6.发明申请公开(公告)号：US20080128629A1
公开(公告)日：2008-06-05
申请号：US12028850
申请日：2008-02-11
IPC分类号： G01T1/02
CPC分类号： G01T1/244
摘要： A method, device and system for monitoring ionizing radiation. The method including: collecting an ionizing radiation induced charge collected by the depletion region of a diode formed in a silicon layer below an oxide layer buried below a surface of a silicon substrate; and coupling a cathode of the diode to a precharged node of a clocked logic circuit such that the ionizing radiation induced charge collected by a depletion region of the diode will discharge the precharged node and change an output state of the clocked logic circuit.
摘要翻译： 一种用于监测电离辐射的方法，装置和系统。 该方法包括：收集由埋在硅衬底表面下方的氧化物层下面的硅层中形成的二极管的耗尽区收集的电离辐射感应电荷; 以及将二极管的阴极耦合到时钟逻辑电路的预充电节点，使得由二极管的耗尽区收集的电离辐射感应电荷将放电预充电节点并改变时钟逻辑电路的输出状态。
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公开(公告)号：US07227239B2
公开(公告)日：2007-06-05
申请号：US10948773
申请日：2004-09-23
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A resettable fuse device is fabricated on one surface of a semiconductor substrate (10) and includes: a gate region (20) having first and second ends; a source node (81) formed in proximity to the first end of the gate region; an extension region (52) formed to connect the source node to the first end of the gate region; and a drain node (80) formed in proximity to the second end of the gate region and separated from the gate region by a distance (D) such that upon application of a predetermined bias voltage to the drain node a connection between the drain node and the second end of the gate region is completed by junction depletion. A gate dielectric (30) and a gate electrode (40) are formed over the gate region. Current flows between the source node and the drain node when the predetermined bias is applied to both the drain node and the gate electrode.
摘要翻译： 在半导体衬底（10）的一个表面上制造可重置熔丝器件，并且包括：具有第一和第二端的栅极区域（20） 源极节点（81），其形成在所述栅极区域的第一端附近; 形成为将源极节点连接到栅极区域的第一端的延伸区域（52） 以及漏极节点（80），其形成在栅极区域的第二端附近，并且与栅极区分离距离（D），使得在向漏极节点施加预定的偏置电压时，漏极节点和 栅极区域的第二端通过结损耗完成。 栅极电介质（30）和栅电极（40）形成在栅极区域上方。 当预定偏压施加到漏极节点和栅电极时，电流在源节点和漏极节点之间流动。
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8.发明授权Device for monitoring ionizing radiation in silicon-on insulator integrated circuits 有权用于监控绝缘体上硅集成电路中的电离辐射的装置公开(公告)号：US07473904B2
公开(公告)日：2009-01-06
申请号：US12028850
申请日：2008-02-11
IPC分类号： H01L31/00
CPC分类号： G01T1/244
摘要： A device and system for monitoring ionizing radiation. The device including: a diode formed in a silicon layer below an oxide layer buried below a surface of a silicon substrate; and a cathode of the diode coupled to a precharged node of a clocked logic circuit, an output state of the clocked logic circuit responsive a change in state of the precharged node, a state of the precharged node responsive to ionizing radiation induced charge collected by a depletion region of the diode and collected in the cathode.
摘要翻译： 用于监测电离辐射的装置和系统。 该器件包括：二极管，其形成在埋在硅衬底的表面下方的氧化物层下方的硅层中; 并且二极管的阴极耦合到时钟逻辑电路的预充电节点，时钟逻辑电路的输出状态响应于预充电节点的状态改变，预充电节点的状态响应于电离辐射诱发的电荷 二极管的耗尽区域并收集在阴极中。
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9.发明授权公开(公告)号：US07375339B2
公开(公告)日：2008-05-20
申请号：US11380736
申请日：2006-04-28
IPC分类号： G01T1/02
CPC分类号： G01T1/244
摘要： A method, device and system for monitoring ionizing radiation. The method including: collecting an ionizing radiation induced charge collected by the depletion region of a diode formed in a silicon layer below an oxide layer buried below a surface of a silicon substrate; and coupling a cathode of the diode to a precharged node of a clocked logic circuit such that the ionizing radiation induced charge collected by a depletion region of the diode will discharge the precharged node and change an output state of the clocked logic circuit.
摘要翻译： 一种用于监测电离辐射的方法，装置和系统。 该方法包括：收集由埋在硅衬底表面下方的氧化物层下面的硅层中形成的二极管的耗尽区收集的电离辐射感应电荷; 以及将二极管的阴极耦合到时钟逻辑电路的预充电节点，使得由二极管的耗尽区收集的电离辐射感应电荷将放电预充电节点并改变时钟逻辑电路的输出状态。
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10.发明授权System and method for measuring circuit performance degradation due to PFET negative bias temperature instability (NBTI) 有权用于测量由PFET负偏压温度不稳定性（NBTI）引起的电路性能退化的系统和方法公开(公告)号：US06731179B2
公开(公告)日：2004-05-04
申请号：US10063295
申请日：2002-04-09
IPC分类号： H03B2700
CPC分类号： H03K5/131 , G01R31/2642 , G01R31/2858 , G01R31/2879 , G01R31/30 , H03K5/133
摘要： A ring oscillator (and test circuit incorporating the ring oscillator and test method therefor) includes an odd number of elements interconnected in a serially-connected infinite loop, each oscillator element having an associated programmable delay feature. The circuit can be used to measure effects of Negative Bias Temperature Instability (NBTI) in p-channel MOSFETs (PFETs).
摘要翻译： 环形振荡器（以及包含环形振荡器的测试电路及其测试方法）包括在串联连接的无限循环中互连的奇数个元件，每个振荡器元件具有相关联的可编程延迟特征。 该电路可用于测量p沟道MOSFET（PFET）中负偏压温度不稳定性（NBTI）的影响。
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