公开(公告)号：US20090035588A1

公开(公告)日：2009-02-05

申请号：US11831005

申请日：2007-07-31

申请人： Wai-Kin Li ,  Yi-Hsiung Lin ,  Gerald Matusiewicz

发明人： Wai-Kin Li ,  Yi-Hsiung Lin ,  Gerald Matusiewicz

IPC分类号： B32B15/04 ,  H01L21/44

CPC分类号： H01L23/5226 ,  H01L21/76808 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/12044 ,  Y10T428/31678 ,  H01L2924/00

摘要： A semiconductor structure and method of manufacturing the semiconductor structure, and more particularly to a semiconductor structure having reduced metal line resistance and a method of manufacturing the same in back end of line (BEOL) processes. The method includes forming a first trench extending to a lower metal layer Mx+1 and forming a second trench remote from the first trench. The method further includes filling the first trench and the second trench with conductive material. The conductive material in the second trench forms a vertical wiring line extending orthogonally and in electrical contact with an upper wiring layer and electrically isolated from lower metal layers including the lower metal layer Mx+1. The vertical wiring line decreases a resistance of a structure.

摘要翻译： 半导体结构和半导体结构的制造方法，更具体地说，涉及具有降低的金属线电阻的半导体结构及其后端（BEOL）工艺的制造方法。 该方法包括形成延伸到下金属层Mx + 1并形成远离第一沟槽的第二沟槽的第一沟槽。 该方法还包括用导电材料填充第一沟槽和第二沟槽。 第二沟槽中的导电材料形成垂直布线，其垂直布线并与上布线层电接触并与包括下金属层Mx + 1的下金属层电隔离。 垂直布线减小了结构的电阻。

公开(公告)号：US08298912B2

公开(公告)日：2012-10-30

申请号：US13080326

申请日：2011-04-05

申请人： Wai-Kin Li ,  Yi-Hsiung Lin ,  Gerald Matusiewicz

发明人： Wai-Kin Li ,  Yi-Hsiung Lin ,  Gerald Matusiewicz

IPC分类号： H01L21/76

CPC分类号： H01L23/5226 ,  H01L21/76808 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/12044 ,  Y10T428/31678 ,  H01L2924/00

摘要： A semiconductor structure and method of manufacturing the semiconductor structure, and more particularly to a semiconductor structure having reduced metal line resistance and a method of manufacturing the same in back end of line (BEOL) processes. The method includes forming a first trench extending to a lower metal layer Mx+1 and forming a second trench remote from the first trench. The method further includes filling the first trench and the second trench with conductive material. The conductive material in the second trench forms a vertical wiring line extending orthogonally and in electrical contact with an upper wiring layer and electrically isolated from lower metal layers including the lower metal layer Mx+1. The vertical wiring line decreases a resistance of a structure.

摘要翻译： 半导体结构和半导体结构的制造方法，更具体地说，涉及具有降低的金属线电阻的半导体结构及其后端（BEOL）工艺的制造方法。 该方法包括形成延伸到下金属层Mx + 1并形成远离第一沟槽的第二沟槽的第一沟槽。 该方法还包括用导电材料填充第一沟槽和第二沟槽。 第二沟槽中的导电材料形成垂直布线，其垂直布线并与上布线层电接触并与包括下金属层Mx + 1的下金属层电隔离。 垂直布线减小了结构的电阻。

公开(公告)号：US20110183491A1

公开(公告)日：2011-07-28

申请号：US13080326

申请日：2011-04-05

申请人： Wai-Kin LI ,  Yi-Hsiung Lin ,  Gerald Matusiewicz

发明人： Wai-Kin LI ,  Yi-Hsiung Lin ,  Gerald Matusiewicz

IPC分类号： H01L21/762

CPC分类号： H01L23/5226 ,  H01L21/76808 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/12044 ,  Y10T428/31678 ,  H01L2924/00

摘要： A semiconductor structure and method of manufacturing the semiconductor structure, and more particularly to a semiconductor structure having reduced metal line resistance and a method of manufacturing the same in back end of line (BEOL) processes. The method includes forming a first trench extending to a lower metal layer Mx+1 and forming a second trench remote from the first trench. The method further includes filling the first trench and the second trench with conductive material. The conductive material in the second trench forms a vertical wiring line extending orthogonally and in electrical contact with an upper wiring layer and electrically isolated from lower metal layers including the lower metal layer Mx+1. The vertical wiring line decreases a resistance of a structure.

摘要翻译： 半导体结构和半导体结构的制造方法，更具体地说，涉及具有降低的金属线电阻的半导体结构及其后端（BEOL）工艺的制造方法。 该方法包括形成延伸到下金属层Mx + 1并形成远离第一沟槽的第二沟槽的第一沟槽。 该方法还包括用导电材料填充第一沟槽和第二沟槽。 第二沟槽中的导电材料形成垂直布线，其垂直布线并与上布线层电接触并与包括下金属层Mx + 1的下金属层电隔离。 垂直布线减小了结构的电阻。

公开(公告)号：US07960036B2

公开(公告)日：2011-06-14

申请号：US11831005

申请日：2007-07-31

申请人： Wai-Kin Li ,  Yi-Hsiung Lin ,  Gerald Matusiewicz

发明人： Wai-Kin Li ,  Yi-Hsiung Lin ,  Gerald Matusiewicz

IPC分类号： B32B9/00 ,  B32B19/00 ,  B32B15/04

CPC分类号： H01L23/5226 ,  H01L21/76808 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/12044 ,  Y10T428/31678 ,  H01L2924/00

摘要： A semiconductor structure and method of manufacturing the semiconductor structure, and more particularly to a semiconductor structure having reduced metal line resistance and a method of manufacturing the same in back end of line (BEOL) processes. The method includes forming a first trench extending to a lower metal layer Mx+1 and forming a second trench remote from the first trench. The method further includes filling the first trench and the second trench with conductive material. The conductive material in the second trench forms a vertical wiring line extending orthogonally and in electrical contact with an upper wiring layer and electrically isolated from lower metal layers including the lower metal layer Mx+1. The vertical wiring line decreases a resistance of a structure.

摘要翻译： 半导体结构和半导体结构的制造方法，更具体地说，涉及具有降低的金属线电阻的半导体结构及其后端（BEOL）工艺的制造方法。 该方法包括形成延伸到下金属层Mx + 1并形成远离第一沟槽的第二沟槽的第一沟槽。 该方法还包括用导电材料填充第一沟槽和第二沟槽。 第二沟槽中的导电材料形成垂直布线，其垂直布线并与上布线层电接触并与包括下金属层Mx + 1的下金属层电隔离。 垂直布线减小了结构的电阻。

公开(公告)号：US20080020327A1

公开(公告)日：2008-01-24

申请号：US11458499

申请日：2006-07-19

申请人： Chih-Chao Yang ,  Wai-Kin Li ,  Yi-Hsiung Lin

发明人： Chih-Chao Yang ,  Wai-Kin Li ,  Yi-Hsiung Lin

IPC分类号： G03F7/26

CPC分类号： H01L21/76808

摘要： A method in which during the formation of damascene features in a semiconductor structure, a planarization material is added to vias formed in the dielectric to protect the vias during subsequent lithographic processing. The planarization material preferred is a developable photosensitive material which can be exposed and developed to define the damascene features rather than etching as is conventional.

摘要翻译： 一种在半导体结构中形成镶嵌特征的方法中，将平坦化材料添加到在电介质中形成的通孔中，以在随后的光刻处理期间保护通孔。 优选的平坦化材料是可显影的感光材料，其可以暴露和显影以限定镶嵌特征，而不是如常规的蚀刻。

公开(公告)号：US07091612B2

公开(公告)日：2006-08-15

申请号：US10684952

申请日：2003-10-14

申请人： Kaushik Kumar ,  Timothy Dalton ,  Larry Clevenger ,  Andy Cowley ,  Douglas C. La Tulipe ,  Mark Hoinkis ,  Chih-Chao Yang ,  Yi-Hsiung Lin ,  Erdem Kaltalioglu ,  Markus Naujok ,  Jochen Schacht

发明人： Kaushik Kumar ,  Timothy Dalton ,  Larry Clevenger ,  Andy Cowley ,  Douglas C. La Tulipe ,  Mark Hoinkis ,  Chih-Chao Yang ,  Yi-Hsiung Lin ,  Erdem Kaltalioglu ,  Markus Naujok ,  Jochen Schacht

IPC分类号： H01L23/12 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L21/76835 ,  H01L21/76811 ,  H01L21/76813 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A dual damascene structure and method of fabrication thereof. An insulating layer comprises a first dielectric material and a second dielectric material, the second dielectric material being different from the first dielectric material. First conductive regions having a first pattern are formed in the first dielectric material, and second conductive regions having a second pattern are formed in the second dielectric material, the second pattern being different from the first pattern. One of the first dielectric material and the second dielectric material comprises an organic material, and the other dielectric material comprises an inorganic material. One of the first and second dielectric materials is etchable selective to the other dielectric material. A method of cleaning a semiconductor wafer processing chamber while a wafer remains residing within the chamber is also disclosed.

公开(公告)号：US20050176237A1

公开(公告)日：2005-08-11

申请号：US10772777

申请日：2004-02-05

申请人： Theodorus Standaert ,  Bernd Kastenmeier ,  Yi-Hsiung Lin ,  Yi-Fang Cheng ,  Larry Clevenger ,  Stephen Greco ,  O Sung Kwon

发明人： Theodorus Standaert ,  Bernd Kastenmeier ,  Yi-Hsiung Lin ,  Yi-Fang Cheng ,  Larry Clevenger ,  Stephen Greco ,  O Sung Kwon

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/76802 ,  H01L21/76867

摘要： In damascene processing, metal hardmask sputtering redeposition that occurs during reactive ion etching (RIE) is exploited to produce, during the RIE process, a desired barrier metal liner on the etched feature.

摘要翻译： 在镶嵌加工中，在反应离子蚀刻（RIE）期间发生的金属硬掩模溅射再沉积被利用以在RIE工艺期间在蚀刻特征上产生期望的阻挡金属衬垫。

公开(公告)号：US06593185B1

公开(公告)日：2003-07-15

申请号：US10150385

申请日：2002-05-17

申请人： Teng-Chun Tsai ,  Chia-Lin Hsu ,  Yi-Fang Cheng ,  Yi-Hsiung Lin

发明人： Teng-Chun Tsai ,  Chia-Lin Hsu ,  Yi-Fang Cheng ,  Yi-Hsiung Lin

IPC分类号： H01L218242

CPC分类号： H01L27/108 ,  H01L28/90

摘要： A method for fabricating a vertical three-dimensional metal-insulator-metal capacitor (MIM capacitor) structure is disclosed. The present invention utilized a vertical three-dimensional MIM capacitor structure on the substrate to decrease the structure area of the MIM capacitor in logic integrated circuit and integration for copper dual damascene process at an identical capacitance on a chip; therefore, the capacitance density of the vertical three-dimensional capacitor can be increased. Furthermore, the present invention is provided a method for fabricating the vertical three-dimensional MIM capacitor structure that compatible with the fabrication of the copper dual damascene structure such that the number of the photomask during the fabrication process can be reduced.

摘要翻译： 公开了一种用于制造垂直三维金属 - 绝缘体 - 金属电容器（MIM电容器）结构的方法。 本发明在衬底上利用垂直三维MIM电容器结构，以降低逻辑集成电路中MIM电容器的结构面积，并在芯片上的相同电容下对铜双镶嵌工艺进行集成; 因此，可以增加垂直三维电容器的电容密度。 此外，本发明提供一种制造与铜双镶嵌结构的制造兼容的垂直三维MIM电容器结构的方法，使得可以减少在制造过程中的光掩模的数量。

公开(公告)号：US20200324239A1

公开(公告)日：2020-10-15

申请号：US16378579

申请日：2019-04-09

申请人： Yi-Hsiung Lin

发明人： Yi-Hsiung Lin

IPC分类号： B01D46/00

摘要： An air cleaner includes a housing, a fan, one or more filtering elements, and a washing system. The housing is provided with an air inlet and an air outlet. The fan is mounted in the housing at a location corresponding to the air outlet and rotated by a motor. The filtering elements are arranged in the housing below the air outlet while above the air inlet. The washing system includes a drain pan, at least one sprinkler, a water tank and a pump, is located in the housing. The drain pan is provided with a drainage port and obliquely arranged below the filtering elements. The sprinkler is arranged above the filtering elements. The water tank and the pump are mounted at a bottom of the housing. An injection pipe is connected to the water tank and extends out of the housing for filling the water tank with water and/or detergent.

公开(公告)号：US20090266517A1

公开(公告)日：2009-10-29

申请号：US12108534

申请日：2008-04-24

申请人： Yi-Hsiung Lin

发明人： Yi-Hsiung Lin

IPC分类号： F28D15/00

CPC分类号： F28D3/02 ,  Y10S261/11

摘要： A cooler includes a body, a water tank installed in the body for storing cooling water, a pump fixed in the water tank, a water pipe connected to the pump and extending upward, a spray pipe connected to the water pipe, at least one gas cooling device located above the spray pipe, at least one fan fixed on top of the body, at least one wind hole formed in a side of the body, at least one cooling pipe uprightly installed in the body and having an upper portion passing through heat-dispersing chips of the gas cooling device and a lower portion passing through heat-dispersing chips of the water cooling device, and at least one water-heat exchanger below the spray pipe and having a heat-dispersing element. The cooler has two stages of cooling by air and water, having a high effect of swift cooling high temperature to low temperature.

摘要翻译： 冷却器包括主体，安装在主体中用于存储冷却水的水箱，固定在水箱中的泵，连接到泵并向上延伸的水管，连接到水管的喷管，至少一个气体 冷却装置，位于喷管上方，固定在主体顶部的至少一个风扇，形成在主体一侧的至少一个风洞，至少一个直立安装在主体中的冷却管，并具有通过热量的上部 - 气体冷却装置的分散芯片和通过水冷装置的散热片的下部，以及喷管下方的至少一个水热交换器，并具有散热元件。 冷却器有两个阶段的空气和水冷却，具有很高的快速冷却高温到低温的效果。