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    Polishing methods and apparatus
    4.
    发明授权
    Polishing methods and apparatus 有权
    抛光方法和设备

    公开(公告)号：US07201634B1

    公开(公告)日：2007-04-10

    申请号：US11273134

    申请日：2005-11-14

    申请人： Markus Naujok ,  Erdem Kaltalioglu

    发明人： Markus Naujok ,  Erdem Kaltalioglu

    IPC分类号： B24B7/22

    CPC分类号： B24B37/015 ,  B24B57/02

    摘要： Apparatus for and methods of chemical mechanical polishing (CMP) of semiconductor wafers are disclosed. A preferred embodiment comprises an apparatus for polishing a semiconductor workpiece that includes a polishing pad, a fluid dispenser adapted to dispense a fluid to the polishing pad, and a temperature measurement device adapted to measure the temperature of the fluid. The apparatus includes a heat exchanger adapted to increase or decrease the temperature of the fluid.

    摘要翻译： 公开了半导体晶片的化学机械抛光（CMP）的设备和方法。 优选实施例包括用于抛光半导体工件的装置，其包括抛光垫，适于将流体分配到抛光垫的流体分配器和适于测量流体温度的温度测量装置。 该装置包括适于增加或降低流体温度的热交换器。

    Composite intermetal dielectric structure including low-k dielectric material
    5.
    发明授权
    Composite intermetal dielectric structure including low-k dielectric material 失效
    复合金属间电介质结构包括低k电介质材料

    公开(公告)号：US07041574B2

    公开(公告)日：2006-05-09

    申请号：US10894259

    申请日：2004-07-19

    申请人： Sun-Oo Kim ,  Markus Naujok ,  Andy Cowley

    发明人： Sun-Oo Kim ,  Markus Naujok ,  Andy Cowley

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76829 ,  H01L21/76835 ,  H01L21/76885 ,  Y10S438/958

    摘要： A method of forming a composite intermetal dielectric structure is provided. An initial intermetal dielectric structure is provided, which includes a first dielectric layer and two conducting lines. The two conducting lines are located in the first dielectric layer. A portion of the first dielectric layer is removed between the conducting lines to form a trench. The trench is filled with a second dielectric material. The second dielectric material is a low-k dielectric having a dielectric constant less than that of the first dielectric layer.

    摘要翻译： 提供了形成复合金属间电介质结构的方法。 提供初始的金属间电介质结构，其包括第一介电层和两条导线。 两条导线位于第一介质层中。 第一介电层的一部分在导线之间被去除以形成沟槽。 沟槽填充有第二电介质材料。 第二电介质材料是具有小于第一介电层的介电常数的介电常数的低k电介质。

    Finishing pad design for multidirectional use
    6.
    发明授权
    Finishing pad design for multidirectional use 失效
    整理垫设计用于多方向使用

    公开(公告)号：US06602123B1

    公开(公告)日：2003-08-05

    申请号：US10243879

    申请日：2002-09-13

    申请人： Markus Naujok

    发明人： Markus Naujok

    IPC分类号： B24D1100

    CPC分类号： B24B37/24

    摘要： A polishing pad (for example, polishing pad 305) for use in polarization of a semiconductor wafer (for example, semiconductor wafer 420), the polishing pad 305 featuring a plurality of different polishing surfaces, depending upon the direction of the movement of the polishing pad 305. The polishing pad 305 may take the form of a polishing disc or a polishing belt. The polarization of the semiconductor wafer 420 can then take place at a fewer number of polishing stations, thereby reducing the amount of time needed and reducing the probability of damage to the semiconductor wafer 420.

    摘要翻译： 用于半导体晶片（例如，半导体晶片420）的偏振的抛光垫（例如，抛光垫305），具有多个不同抛光表面的抛光垫305，其取决于抛光的移动方向 抛光垫305可以采取抛光盘或抛光带的形式。 然后半导体晶片420的极化可以在较少数量的抛光站进行，从而减少所需的时间量并降低对半导体晶片420的损坏概率。

    Semiconductor devices and structures thereof
    7.
    发明授权
    Semiconductor devices and structures thereof 有权
    半导体器件及其结构

    公开(公告)号：US08013364B2

    公开(公告)日：2011-09-06

    申请号：US12579807

    申请日：2009-10-15

    申请人： Markus Naujok ,  Hermann Wendt ,  Alois Gutmann ,  Muhammed Shafi Pallachalil

    发明人： Markus Naujok ,  Hermann Wendt ,  Alois Gutmann ,  Muhammed Shafi Pallachalil

    IPC分类号： H01L23/52

    CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A structure having air gaps between interconnects is disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region.

    摘要翻译： 公开了一种在互连之间具有气隙的结构。 第一绝缘材料沉积在工件上，并且具有牺牲部分的第二绝缘材料沉积在第一绝缘材料上。 导电线形成在第一和第二绝缘层中。 处理第二绝缘材料以去除牺牲部分，并且去除第一绝缘材料的至少一部分，在导线之间形成气隙。 第二绝缘材料在处理它以去除牺牲部分之后是不可渗透的并且是可渗透的。 工件的第一区域可以在处理期间被掩蔽，使得第二绝缘材料在工件的第二区域变得可渗透，但在第一区域中仍然不可渗透，从而允许在第二区域中形成气隙，但是 不是第一个地区。

    Methods of manufacturing semiconductor devices and structures thereof
    8.
    发明授权
    Methods of manufacturing semiconductor devices and structures thereof 有权
    制造半导体器件的方法及其结构

    公开(公告)号：US07629225B2

    公开(公告)日：2009-12-08

    申请号：US11151134

    申请日：2005-06-13

    申请人： Markus Naujok ,  Hermann Wendt ,  Alois Gutmann ,  Muhammed Shafi Pallachalil

    发明人： Markus Naujok ,  Hermann Wendt ,  Alois Gutmann ,  Muhammed Shafi Pallachalil

    IPC分类号： H01L21/76

    CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods of forming air gaps between interconnects of integrated circuits and structures thereof are disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region.

    摘要翻译： 公开了在集成电路的互连和其结构之间形成气隙的方法。 第一绝缘材料沉积在工件上，并且具有牺牲部分的第二绝缘材料沉积在第一绝缘材料上。 导电线形成在第一和第二绝缘层中。 处理第二绝缘材料以去除牺牲部分，并且去除第一绝缘材料的至少一部分，在导线之间形成气隙。 第二绝缘材料在处理它以去除牺牲部分之后是不可渗透的并且是可渗透的。 工件的第一区域可以在处理期间被掩蔽，使得第二绝缘材料在工件的第二区域变得可渗透，但在第一区域中仍然不可渗透，从而允许在第二区域中形成气隙，但是 不是第一个地区。

    Methods of forming integrated circuit devices having metal interconnect layers therein
    9.
    发明授权
    Methods of forming integrated circuit devices having metal interconnect layers therein 有权

    公开(公告)号：US07282451B2

    公开(公告)日：2007-10-16

    申请号：US11216686

    申请日：2005-08-31

    申请人： Duk Ho Hong ,  Kyoung Woo Lee ,  Markus Naujok ,  Roman Knoefler

    发明人： Duk Ho Hong ,  Kyoung Woo Lee ,  Markus Naujok ,  Roman Knoefler

    IPC分类号： H01L21/302

    CPC分类号： C25D5/022 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods of forming metal interconnect layers include forming an electrically insulating layer having a contact hole therein, on a semiconductor substrate and then forming a recess in the electrically insulating layer, at a location adjacent the contact hole. The contact hole and the recess are then filled with a first electrically conductive material (e.g., tungsten (W)). At least a portion of the first electrically conductive material within the contact hole is then exposed. This exposure occurs by etching back a portion of the electrically insulating layer using the first electrically conductive material within the contact hole and within the recess as an etching mask. The first electrically conductive material within the recess is then removed to expose another portion of the electrically insulating layer. Following this, the exposed portion of the first electrically conductive material is covered with a second electrically conductive material (e.g., copper (Cu)), which directly contacts the exposed portion of the first electrically conductive material. This covering step results in the definition of a wiring pattern including the first and second electrically conductive materials.

    Finishing pad design for multidirectional use
    10.
    发明授权
    Finishing pad design for multidirectional use 失效
    整理垫设计用于多方向使用

    公开(公告)号：US06761620B2

    公开(公告)日：2004-07-13

    申请号：US10436007

    申请日：2003-05-12

    申请人： Markus Naujok

    发明人： Markus Naujok

    IPC分类号： B24B100

    CPC分类号： B24B37/24

    摘要： A polishing pad (for example, polishing pad 305) for use in planarization of a semiconductor wafer (for example, semiconductor wafer 420), the polishing pad 305 featuring a plurality of different polishing surfaces, depending upon the direction of the movement of the polishing pad 305. The polishing pad 305 may take the form of a polishing disc or a polishing belt. The planarization of the semiconductor wafer 420 can then take place at a fewer number of polishing stations, thereby reducing the amount of time needed and reducing the probability of damage to the semiconductor wafer 420.

    摘要翻译： 用于半导体晶片（例如，半导体晶片420）的平坦化的抛光垫（例如抛光垫305），具有多个不同抛光表面的抛光垫305，其取决于抛光的移动方向 抛光垫305可以采取抛光盘或抛光带的形式。 然后半导体晶片420的平坦化可以在较少数量的抛光站进行，从而减少所需的时间量并降低对半导体晶片420的损坏概率。