公开(公告)号：US08880965B2

公开(公告)日：2014-11-04

申请号：US13682749

申请日：2012-11-21

申请人： Wanggen Zhang ,  Sian Lu ,  Shayan Zhang

发明人： Wanggen Zhang ,  Sian Lu ,  Shayan Zhang

IPC分类号： G01R31/28

CPC分类号： G01R31/318541

摘要： A low power scan flip-flop cell includes a multiplexer, a master latch, a scan slave latch and a data slave latch. The master latch is connected to the multiplexer, and used for generating a first latch signal. The scan slave latch is connected to the master latch, and generates a scan output (SO) signal. The data slave latch is connected to the master latch, and generates a Q output depending on a scan enable (SE) input signal and the first latch signal. The Q output is maintained at a predetermined level during scan mode, which eliminates unnecessary switching of combinational logic connected to the scan flip-flop cell and thus reduces power consumption.

摘要翻译： 低功率扫描触发器单元包括多路复用器，主锁存器，扫描从锁存器和数据从锁存器。 主锁存器连接到多路复用器，用于产生第一个锁存信号。 扫描从锁存器连接到主锁存器，并产生扫描输出（SO）信号。 数据从锁存器连接到主锁存器，并根据扫描使能（SE）输入信号和第一锁存信号产生Q输出。 在扫描模式期间，Q输出保持在预定电平，这消除了连接到扫描触发器单元的组合逻辑的不必要的切换，从而降低功耗。

公开(公告)号：US20140040688A1

公开(公告)日：2014-02-06

申请号：US13682749

申请日：2012-11-21

申请人： Wanggen Zhang ,  Sian Lu ,  Shayan Zhang

发明人： Wanggen Zhang ,  Sian Lu ,  Shayan Zhang

IPC分类号： G01R31/3177

CPC分类号： G01R31/318541

摘要： A low power scan flip-flop cell includes a multiplexer, a master latch, a scan slave latch and a data slave latch. The master latch is connected to the multiplexer, and used for generating a first latch signal. The scan slave latch is connected to the master latch, and generates a scan output (SO) signal. The data slave latch is connected to the master latch, and generates a Q output depending on a scan enable (SE) input signal and the first latch signal. The Q output is maintained at a predetermined level during scan mode, which eliminates unnecessary switching of combinational logic connected to the scan flip-flop cell and thus reduces power consumption.

摘要翻译： 低功率扫描触发器单元包括多路复用器，主锁存器，扫描从锁存器和数据从锁存器。 主锁存器连接到多路复用器，用于产生第一个锁存信号。 扫描从锁存器连接到主锁存器，并产生扫描输出（SO）信号。 数据从锁存器连接到主锁存器，并根据扫描使能（SE）输入信号和第一锁存信号产生Q输出。 在扫描模式期间，Q输出保持在预定电平，这消除了连接到扫描触发器单元的组合逻辑的不必要的切换，从而降低功耗。

公开(公告)号：US20130300497A1

公开(公告)日：2013-11-14

申请号：US13609283

申请日：2012-09-11

申请人： Xu Zhang ,  Chad J. Lerma ,  Kai Liu ,  Sian Lu ,  Hao Wang ,  Shayan Zhang ,  Wanggen Zhang

发明人： Xu Zhang ,  Chad J. Lerma ,  Kai Liu ,  Sian Lu ,  Hao Wang ,  Shayan Zhang ,  Wanggen Zhang

IPC分类号： H01L25/00

CPC分类号： H03K19/177 ,  H01L2224/48137 ,  H01L2224/49171 ,  H03K19/17744

摘要： A reconfigurable integrated circuit (IC) has IC interface terminals including circuit input terminals and circuit output terminals. A bypass controller and bypass circuitry are coupled to each other, and to at least one of the circuit input terminals and at least one of the circuit output terminals. A processing circuit has multiple circuit modules coupled to the bypass circuitry. The processing circuit is coupled to at least one of the circuit input terminals and at least one of the circuit output terminals. In operation the bypass controller controls the bypass circuitry to selectively couple at least one pair of the IC interface terminals together, the pair including one of the circuit input terminals and one of the circuit output terminals. When the pair of IC interface terminals are coupled together, at least one of the circuit modules is selectively de-coupled from the pair of the IC terminals.

摘要翻译： 可重构集成电路（IC）具有包括电路输入端子和电路输出端子的IC接口端子。 旁路控制器和旁路电路彼此耦合，并且耦合到至少一个电路输入端子和至少一个电路输出端子。 处理电路具有耦合到旁路电路的多个电路模块。 处理电路耦合到至少一个电路输入端和至少一个电路输出端。 在操作中，旁路控制器控制旁路电路以选择性地将至少一对IC接口端子耦合在一起，该对包括电路输入端子之一和电路输出端子之一。 当一对IC接口端子耦合在一起时，至少一个电路模块被选择性地从一对IC端子去耦合。

公开(公告)号：US08736302B2

公开(公告)日：2014-05-27

申请号：US13609283

申请日：2012-09-11

申请人： Xu Zhang ,  Chad J. Lerma ,  Kai Liu ,  Sian Lu ,  Hao Wang ,  Shayan Zhang ,  Wanggen Zhang

发明人： Xu Zhang ,  Chad J. Lerma ,  Kai Liu ,  Sian Lu ,  Hao Wang ,  Shayan Zhang ,  Wanggen Zhang

IPC分类号： H03K19/173 ,  H03K19/00 ,  H01L25/00

CPC分类号： H03K19/177 ,  H01L2224/48137 ,  H01L2224/49171 ,  H03K19/17744

摘要： A reconfigurable integrated circuit (IC) has IC interface terminals including circuit input terminals and circuit output terminals. A bypass controller and bypass circuitry are coupled to each other, and to at least one of the circuit input terminals and at least one of the circuit output terminals. A processing circuit has multiple circuit modules coupled to the bypass circuitry. The processing circuit is coupled to at least one of the circuit input terminals and at least one of the circuit output terminals. In operation the bypass controller controls the bypass circuitry to selectively couple at least one pair of the IC interface terminals together, the pair including one of the circuit input terminals and one of the circuit output terminals. When the pair of IC interface terminals are coupled together, at least one of the circuit modules is selectively de-coupled from the pair of the IC terminals.

摘要翻译： 可重构集成电路（IC）具有包括电路输入端子和电路输出端子的IC接口端子。 旁路控制器和旁路电路彼此耦合，并且耦合到至少一个电路输入端子和至少一个电路输出端子。 处理电路具有耦合到旁路电路的多个电路模块。 处理电路耦合到至少一个电路输入端和至少一个电路输出端。 在操作中，旁路控制器控制旁路电路以选择性地将至少一对IC接口端子耦合在一起，该对包括电路输入端子之一和电路输出端子之一。 当一对IC接口端子耦合在一起时，至少一个电路模块被选择性地从一对IC端子去耦合。

公开(公告)号：US20160091566A1

公开(公告)日：2016-03-31

申请号：US14580237

申请日：2014-12-23

申请人： Sian Lu ,  Hao Wang

发明人： Sian Lu ,  Hao Wang

IPC分类号： G01R31/3177

CPC分类号： G01R31/3177 ,  G01R31/318541 ,  G01R31/318594 ,  H03K3/012

摘要： A scan-testable integrated circuit includes first and second flip-flops. The first flip-flop includes first and second latches and the second flip-flop includes third and fourth latches and a logic circuit. During scan-shift mode of scan testing, the first flip-flop shifts a first bit of a test pattern into the second flip-flop. The first flip-flop then shifts a second bit of the test pattern into the second flip-flop. The logic circuit deactivates a clock signal provided to the third latch, which is a master latch, when the logic states of the first and second bits are equal. The output terminals of the third and fourth latches are retained at the logic state corresponding to the first bit, thereby reducing power consumption.

摘要翻译： 可扫描的集成电路包括第一和第二触发器。 第一触发器包括第一和第二锁存器，第二触发器包括第三和第四锁存器和逻辑电路。 在扫描测试的扫描移位模式期间，第一触发器将测试图案的第一位移位到第二触发器中。 然后，第一触发器将测试图案的第二位移到第二触发器中。 当第一和第二位的逻辑状态相等时，逻辑电路去激活提供给作为主锁存器的第三锁存器的时钟信号。 第三和第四锁存器的输出端子保持在与第一位相对应的逻辑状态，从而降低功耗。

公开(公告)号：US09291674B1

公开(公告)日：2016-03-22

申请号：US14580237

申请日：2014-12-23

申请人： Sian Lu ,  Hao Wang

发明人： Sian Lu ,  Hao Wang

IPC分类号： G01R31/28 ,  G01R31/3177 ,  G01R31/3185 ,  H03K3/012

CPC分类号： G01R31/3177 ,  G01R31/318541 ,  G01R31/318594 ,  H03K3/012

摘要： A scan-testable integrated circuit includes first and second flip-flops. The first flip-flop includes first and second latches and the second flip-flop includes third and fourth latches and a logic circuit. During scan-shift mode of scan testing, the first flip-flop shifts a first bit of a test pattern into the second flip-flop. The first flip-flop then shifts a second bit of the test pattern into the second flip-flop. The logic circuit deactivates a clock signal provided to the third latch, which is a master latch, when the logic states of the first and second bits are equal. The output terminals of the third and fourth latches are retained at the logic state corresponding to the first bit, thereby reducing power consumption.

摘要翻译： 可扫描的集成电路包括第一和第二触发器。 第一触发器包括第一和第二锁存器，第二触发器包括第三和第四锁存器和逻辑电路。 在扫描测试的扫描移位模式期间，第一触发器将测试图案的第一位移位到第二触发器中。 然后，第一触发器将测试图案的第二位移到第二触发器中。 当第一和第二位的逻辑状态相等时，逻辑电路去激活提供给作为主锁存器的第三锁存器的时钟信号。 第三和第四锁存器的输出端子保持在与第一位相对应的逻辑状态，从而降低功耗。