公开(公告)号：US06359630B1

公开(公告)日：2002-03-19

申请号：US09332734

申请日：1999-06-14

申请人： Wayne Morse ,  Michael F. Deering ,  Mike Lavelle ,  Ewa Kubalska ,  Huang Pan ,  Scott R. Nelson

发明人： Wayne Morse ,  Michael F. Deering ,  Mike Lavelle ,  Ewa Kubalska ,  Huang Pan ,  Scott R. Nelson

IPC分类号： G06T1530

CPC分类号： G06T15/30 ,  G09G5/393

摘要： A method and computer graphics system for clip testing using clip bits stored in a general-purpose register for each vertex of a geometric primitive. In one embodiment, a rendering unit or other processor sets bits in a clip bits register for each vertex of a geometric primitive. Each bit indicates whether the vertex is inside or outside of a clipping boundary with respect to a particular clipping plane. A frame buffer controller or other graphics processor performs clip testing on the entire geometric primitive by performing Boolean operations on the clip bits. The frame buffer controller may trivially accept or trivially reject the primitive based on the clip testing. If the primitive cannot be trivially rejected or trivially accepted, then the frame buffer controller sends an interrupt to the rendering unit. The rendering unit reads an exception register to determine that the reason for the interrupt is the need to clip the primitive. The rendering unit reads the vertices from the frame buffer controller, clips the primitive, and sends the new vertices to the frame buffer controller. The frame buffer controller clears the interrupt and resumes its graphics processing.

摘要翻译： 一种方法和计算机图形系统，用于使用存储在通用寄存器中的剪辑位来进行几何图元的每个顶点的剪辑测试。 在一个实施例中，渲染单元或其他处理器针对几何图元的每个顶点设置剪辑位寄存器中的位。 每个位指示顶点是否相对于特定剪切平面在剪切边界内部或外部。 帧缓冲控制器或其他图形处理器通过对剪辑位执行布尔运算来对整个几何图元执行剪辑测试。 帧缓冲控制器可以基于剪辑测试轻易地接受或简单地拒绝原语。 如果不能简单地拒绝或简单地接受原语，则帧缓冲控制器向渲染单元发送中断。 渲染单元读取一个异常寄存器，以确定中断的原因是需要剪切图元。 渲染单元从帧缓冲器控制器读取顶点，剪切原始图像，并将新顶点发送到帧缓冲控制器。 帧缓冲控制器清除中断并恢复其图形处理。

公开(公告)号：US20090256607A1

公开(公告)日：2009-10-15

申请号：US12101028

申请日：2008-04-10

申请人： Brian Smith ,  Ewa Kubalska

发明人： Brian Smith ,  Ewa Kubalska

IPC分类号： H03K3/02

CPC分类号： G06F1/32

摘要： In an integrated circuit device, a power circuit for maintaining asserted values on an input output pin of the device when a functional block of the device is placed in a sleep mode. The device includes a power circuit disposed along the periphery of the device, the power circuit configured to maintain power when the device is placed in a low-power mode. A plurality of input output blocks are included in the device and are for receiving external inputs for the integrated circuit device and for providing outputs from the integrated circuit device. The power circuit is coupled to provide power to at least one of the input output blocks to maintain state when the integrated circuit device is in the low-power mode.

摘要翻译： 在集成电路器件中，当器件的功能块处于休眠模式时，用于在器件的输入输出引脚上维持有效值的电源电路。 该装置包括沿该装置的周边设置的电源电路，该电源电路配置成当该装置处于低功率模式时保持电力。 在设备中包括多个输入输出块，并且用于接收用于集成电路器件的外部输入并用于提供来自集成电路器件的输出。 电源电路被耦合以向至少一个输入输出块提供电力，以在集成电路器件处于低功率模式时维持状态。

公开(公告)号：US09423846B2

公开(公告)日：2016-08-23

申请号：US12101028

申请日：2008-04-10

申请人： Brian Smith ,  Ewa Kubalska

发明人： Brian Smith ,  Ewa Kubalska

IPC分类号： G06F1/00 ,  G06F1/26 ,  G06F1/32

CPC分类号： G06F1/32

摘要： In an integrated circuit device, a power circuit for maintaining asserted values on an input output pin of the device when a functional block of the device is placed in a sleep mode. The device includes a power circuit disposed along the periphery of the device, the power circuit configured to maintain power when the device is placed in a low-power mode. A plurality of input output blocks are included in the device and are for receiving external inputs for the integrated circuit device and for providing outputs from the integrated circuit device. The power circuit is coupled to provide power to at least one of the input output blocks to maintain state when the integrated circuit device is in the low-power mode.

摘要翻译： 在集成电路器件中，当器件的功能块处于休眠模式时，用于在器件的输入输出引脚上维持有效值的电源电路。 该装置包括沿该装置的周边设置的电源电路，该电源电路配置成当该装置处于低功率模式时保持电力。 在设备中包括多个输入输出块，并且用于接收用于集成电路器件的外部输入并用于提供来自集成电路器件的输出。 电源电路被耦合以向至少一个输入输出块提供电力，以在集成电路器件处于低功率模式时维持状态。

公开(公告)号：US20090204834A1

公开(公告)日：2009-08-13

申请号：US12029346

申请日：2008-02-11

申请人： Neil Hendin ,  Ewa Kubalska ,  Zahid Najam ,  Stephane Le Provost ,  Brian Smith

发明人： Neil Hendin ,  Ewa Kubalska ,  Zahid Najam ,  Stephane Le Provost ,  Brian Smith

IPC分类号： G06F1/32

CPC分类号： G06F1/22

摘要： A system and method for waking up a portion of a programmable system on a chip (SoC). The system includes a power management unit for controlling power levels to the SoC and one or more inputs for receiving inputs from a coupled device. The system further includes a power management interface coupled to the one or more inputs. The power management interface signals the power management unit to adjust power levels to the SoC in response to receiving a signal via the one or more inputs corresponding to a wake event.

摘要翻译： 用于唤醒芯片上可编程系统（SoC）的一部分的系统和方法。 该系统包括用于控制对SoC的功率电平的功率管理单元和用于从耦合设备接收输入的一个或多个输入。 该系统还包括耦合到一个或多个输入的电源管理接口。 功率管理接口通过经由与唤醒事件相对应的一个或多个输入来接收信号，向电力管理单元发出信号以调整SoC的功率电平。