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    SYSTEM AND METHOD FOR USING INPUTS AS WAKE SIGNALS
    1.
    发明申请
    SYSTEM AND METHOD FOR USING INPUTS AS WAKE SIGNALS 审中-公开
    使用输入信号作为信号的系统和方法

    公开(公告)号：US20090204834A1

    公开(公告)日：2009-08-13

    申请号：US12029346

    申请日：2008-02-11

    申请人： Neil Hendin ,  Ewa Kubalska ,  Zahid Najam ,  Stephane Le Provost ,  Brian Smith

    发明人： Neil Hendin ,  Ewa Kubalska ,  Zahid Najam ,  Stephane Le Provost ,  Brian Smith

    IPC分类号： G06F1/32

    CPC分类号： G06F1/22

    摘要： A system and method for waking up a portion of a programmable system on a chip (SoC). The system includes a power management unit for controlling power levels to the SoC and one or more inputs for receiving inputs from a coupled device. The system further includes a power management interface coupled to the one or more inputs. The power management interface signals the power management unit to adjust power levels to the SoC in response to receiving a signal via the one or more inputs corresponding to a wake event.

    摘要翻译： 用于唤醒芯片上可编程系统（SoC）的一部分的系统和方法。 该系统包括用于控制对SoC的功率电平的功率管理单元和用于从耦合设备接收输入的一个或多个输入。 该系统还包括耦合到一个或多个输入的电源管理接口。 功率管理接口通过经由与唤醒事件相对应的一个或多个输入来接收信号，向电力管理单元发出信号以调整SoC的功率电平。

    Integrated circuit device core power down independent of peripheral device operation
    2.
    发明授权
    Integrated circuit device core power down independent of peripheral device operation 有权
    集成电路设备核心掉电独立于外围设备运行

    公开(公告)号：US08327173B2

    公开(公告)日：2012-12-04

    申请号：US12002711

    申请日：2007-12-17

    申请人： Neil Hendin ,  Zahid Najam ,  Stephane Le Provost ,  Brian Smith

    发明人： Neil Hendin ,  Zahid Najam ,  Stephane Le Provost ,  Brian Smith

    IPC分类号： G06F1/00

    CPC分类号： G06F1/22 ,  G06F1/3203 ,  G06F1/3287 ,  Y02D10/171 ,  Y02D50/20

    摘要： In an integrated circuit device, a circuit for maintaining asserted values on an input output pin of the device when a functional block of the device is placed in a sleep mode. The circuit includes an interface for coupling a functional block of a processor to an input and output pin and an output storage element coupled to the interface for storing a current value of the input output pin. The circuit further includes a sleep mode enable for controlling the output storage element to store the current value of the input output pin prior to the functional block being entering a sleep mode and cause the current value of the input output pin to remain asserted after the functional block is in sleep mode. The sleep mode enable is also to deactivate the storage element when the sleep mode is exited.

    摘要翻译： 在集成电路器件中，当器件的功能块处于休眠模式时，用于在器件的输入输出引脚上维持有效值的电路。 该电路包括用于将处理器的功能块耦合到输入和输出引脚的接口和耦合到接口的输出存储元件，用于存储输入输出引脚的当前值。 电路还包括睡眠模式使能，用于在功能块进入休眠模式之前控制输出存储元件以存储输入输出引脚的当前值，并且使得输入输出引脚的当前值在功能块之后保持断言 块处于睡眠模式。 睡眠模式启用也是在休眠模式退出时停用存储元件。

    Integrated circuit device core power down independent of peripheral device operation
    3.
    发明申请
    Integrated circuit device core power down independent of peripheral device operation 有权
    集成电路设备核心掉电独立于外围设备运行

    公开(公告)号：US20090153211A1

    公开(公告)日：2009-06-18

    申请号：US12002711

    申请日：2007-12-17

    申请人： Neil Hendin ,  Zahid Najam ,  Stephane Le Provost ,  Brian Smith

    发明人： Neil Hendin ,  Zahid Najam ,  Stephane Le Provost ,  Brian Smith

    IPC分类号： H03K3/02

    CPC分类号： G06F1/22 ,  G06F1/3203 ,  G06F1/3287 ,  Y02D10/171 ,  Y02D50/20

    摘要： In an integrated circuit device, a circuit for maintaining asserted values on an input output pin of the device when a functional block of the device is placed in a sleep mode. The circuit includes an interface for coupling a functional block of a processor to an input and output pin and an output storage element coupled to the interface for storing a current value of the input output pin. The circuit further includes a sleep mode enable for controlling the output storage element to store the current value of the input output pin prior to the functional block being entering a sleep mode and cause the current value of the input output pin to remain asserted after the functional block is in sleep mode. The sleep mode enable is also to deactivate the storage element when the sleep mode is exited.

    摘要翻译： 在集成电路器件中，当器件的功能块处于休眠模式时，用于在器件的输入输出引脚上维持有效值的电路。 该电路包括用于将处理器的功能块耦合到输入和输出引脚的接口和耦合到接口的输出存储元件，用于存储输入输出引脚的当前值。 电路还包括睡眠模式使能，用于在功能块进入休眠模式之前控制输出存储元件以存储输入输出引脚的当前值，并且使得输入输出引脚的当前值在功能块之后保持断言 块处于睡眠模式。 睡眠模式启用也是在休眠模式退出时停用存储元件。

    INTEGRATED CIRCUIT DEVICE HAVING POWER DOMAINS AND PARTITIONS BASED ON USE CASE POWER OPTIMIZATION
    4.
    发明申请
    INTEGRATED CIRCUIT DEVICE HAVING POWER DOMAINS AND PARTITIONS BASED ON USE CASE POWER OPTIMIZATION 有权
    基于使用电源优化的具有电源域和分区的集成电路设备

    公开(公告)号：US20090201082A1

    公开(公告)日：2009-08-13

    申请号：US12029404

    申请日：2008-02-11

    申请人： Brian Smith ,  Parthasarathy Sriram ,  Stephane Le Provost

    发明人： Brian Smith ,  Parthasarathy Sriram ,  Stephane Le Provost

    IPC分类号： G05F1/10

    CPC分类号： G06F1/3203 ,  G06F1/3287 ,  Y02D10/171

    摘要： A programmable SoC (system on a chip) having optimized power domains and power islands. The SoC is an integrated circuit device including a plurality of power domains, each of the power domains having a respective voltage rail to supply power to the power domain. A plurality of power islands are included within the integrated circuit device, wherein each power domain includes at least one power island. A plurality of functional blocks are included within the integrated circuit device, wherein each power island includes at least one functional block. Each functional block is configured to provide a specific device functionality. The integrated circuit device adjusts power consumption in relation to a requested device functionality by individually turning on or turning off power to a selected one or more power domains, and for each turned on power domain, individually power gating one or more power islands.

    摘要翻译： 具有优化的电源域和电源岛的可编程SoC（片上系统）。 SoC是包括多个功率域的集成电路器件，每个电源域具有相应的电压轨，以向电源域供电。 多个功率岛包括在集成电路器件内，其中每个功率域包括至少一个功率岛。 多个功能块包括在集成电路器件内，其中每个功率岛包括至少一个功能块。 每个功能块被配置为提供特定的设备功能。 集成电路装置通过单独打开或关闭所选择的一个或多个功率域的功率来调整与所请求的装置功能相关的功率消耗，并且对于每个打开的功率域，单独地对一个或多个功率岛进行供电。

    Integrated circuit device having power domains and partitions based on use case power optimization
    5.
    发明授权
    Integrated circuit device having power domains and partitions based on use case power optimization 有权
    具有功率域和基于用例功率优化的分区的集成电路器件

    公开(公告)号：US09411390B2

    公开(公告)日：2016-08-09

    申请号：US12029404

    申请日：2008-02-11

    申请人： Brian Smith ,  Parthasarathy Sriram ,  Stephane Le Provost

    发明人： Brian Smith ,  Parthasarathy Sriram ,  Stephane Le Provost

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3203 ,  G06F1/3287 ,  Y02D10/171

    摘要： A programmable SoC (system on a chip) having optimized power domains and power islands. The SoC is an integrated circuit device including a plurality of power domains, each of the power domains having a respective voltage rail to supply power to the power domain. A plurality of power islands are included within the integrated circuit device, wherein each power domain includes at least one power island. A plurality of functional blocks are included within the integrated circuit device, wherein each power island includes at least one functional block. Each functional block is configured to provide a specific device functionality. The integrated circuit device adjusts power consumption in relation to a requested device functionality by individually turning on or turning off power to a selected one or more power domains, and for each turned on power domain, individually power gating one or more power islands.

    摘要翻译： 具有优化的电源域和电源岛的可编程SoC（片上系统）。 SoC是包括多个功率域的集成电路器件，每个电源域具有相应的电压轨，以向电源域供电。 多个功率岛包括在集成电路器件内，其中每个功率域包括至少一个功率岛。 多个功能块包括在集成电路器件内，其中每个功率岛包括至少一个功能块。 每个功能块被配置为提供特定的设备功能。 集成电路装置通过单独打开或关闭所选择的一个或多个功率域的功率来调整与所请求的装置功能相关的功率消耗，并且对于每个打开的功率域，单独地对一个或多个功率岛进行供电。

    USE METHODS FOR POWER OPTIMIZATION USING AN INTEGRATED CIRCUIT HAVING POWER DOMAINS AND PARTITIONS
    6.
    发明申请
    USE METHODS FOR POWER OPTIMIZATION USING AN INTEGRATED CIRCUIT HAVING POWER DOMAINS AND PARTITIONS 审中-公开
    使用具有电源域和分区的集成电路的电源优化的使用方法

    公开(公告)号：US20090204835A1

    公开(公告)日：2009-08-13

    申请号：US12029442

    申请日：2008-02-11

    申请人： Brian Smith ,  Parthasarathy Sriram ,  Stephane Le Provost

    发明人： Brian Smith ,  Parthasarathy Sriram ,  Stephane Le Provost

    IPC分类号： G06F1/32 ,  G06F1/00

    CPC分类号： G06F1/3203 ,  G06F1/3287 ,  Y02D10/171

    摘要： In a programmable SoC (system-on-a-chip) integrated circuit device, a method for optimizing power efficiency for a requested device functionality. The method includes determining a requested device functionality, and in response to the requested device functionality, turning on power for a selected one or more power domains out of a plurality of power domains included within the integrated circuit device. Each of the power domains has its own respective voltage rail to obtain power. The method further includes turning on one or more power islands out of a plurality of power islands included within the integrated circuit device. The requested device functionality is then implemented using one or more functional blocks wherein each functional block is configured to provide a specific device functionality.

    摘要翻译： 在可编程SoC（片上系统）集成电路器件中，一种用于优化所请求的器件功能的功率效率的方法。 该方法包括确定所请求的设备功能，以及响应于所请求的设备功能，为包括在集成电路设备内的多个电力域中的所选择的一个或多个电力域开启电力。 每个电源域具有各自的电压轨以获得电力。 该方法还包括将包含在集成电路器件内的多个功率岛中的一个或多个功率岛接通。 然后使用一个或多个功能块来实现所请求的设备功能，其中每个功能块被配置为提供特定的设备功能。

    Powered ring to maintain IO state independent of the core of an integrated circuit device
    7.
    发明授权
    Powered ring to maintain IO state independent of the core of an integrated circuit device 有权
    电源环保持独立于集成电路器件核心的IO状态

    公开(公告)号：US09423846B2

    公开(公告)日：2016-08-23

    申请号：US12101028

    申请日：2008-04-10

    申请人： Brian Smith ,  Ewa Kubalska

    发明人： Brian Smith ,  Ewa Kubalska

    IPC分类号： G06F1/00 ,  G06F1/26 ,  G06F1/32

    CPC分类号： G06F1/32

    摘要： In an integrated circuit device, a power circuit for maintaining asserted values on an input output pin of the device when a functional block of the device is placed in a sleep mode. The device includes a power circuit disposed along the periphery of the device, the power circuit configured to maintain power when the device is placed in a low-power mode. A plurality of input output blocks are included in the device and are for receiving external inputs for the integrated circuit device and for providing outputs from the integrated circuit device. The power circuit is coupled to provide power to at least one of the input output blocks to maintain state when the integrated circuit device is in the low-power mode.

    摘要翻译： 在集成电路器件中，当器件的功能块处于休眠模式时，用于在器件的输入输出引脚上维持有效值的电源电路。 该装置包括沿该装置的周边设置的电源电路，该电源电路配置成当该装置处于低功率模式时保持电力。 在设备中包括多个输入输出块，并且用于接收用于集成电路器件的外部输入并用于提供来自集成电路器件的输出。 电源电路被耦合以向至少一个输入输出块提供电力，以在集成电路器件处于低功率模式时维持状态。

    POWERED RING TO MAINTAIN IO INDEPENDENT OF THE CORE OF AN INTEGRATED CIRCUIT DEVICE
    8.
    发明申请
    POWERED RING TO MAINTAIN IO INDEPENDENT OF THE CORE OF AN INTEGRATED CIRCUIT DEVICE 有权
    用于维护独立于集成电路设备核心的IO的环

    公开(公告)号：US20090256607A1

    公开(公告)日：2009-10-15

    申请号：US12101028

    申请日：2008-04-10

    申请人： Brian Smith ,  Ewa Kubalska

    发明人： Brian Smith ,  Ewa Kubalska

    IPC分类号： H03K3/02

    CPC分类号： G06F1/32

    摘要： In an integrated circuit device, a power circuit for maintaining asserted values on an input output pin of the device when a functional block of the device is placed in a sleep mode. The device includes a power circuit disposed along the periphery of the device, the power circuit configured to maintain power when the device is placed in a low-power mode. A plurality of input output blocks are included in the device and are for receiving external inputs for the integrated circuit device and for providing outputs from the integrated circuit device. The power circuit is coupled to provide power to at least one of the input output blocks to maintain state when the integrated circuit device is in the low-power mode.

    摘要翻译： 在集成电路器件中，当器件的功能块处于休眠模式时，用于在器件的输入输出引脚上维持有效值的电源电路。 该装置包括沿该装置的周边设置的电源电路，该电源电路配置成当该装置处于低功率模式时保持电力。 在设备中包括多个输入输出块，并且用于接收用于集成电路器件的外部输入并用于提供来自集成电路器件的输出。 电源电路被耦合以向至少一个输入输出块提供电力，以在集成电路器件处于低功率模式时维持状态。