公开(公告)号：US07291923B1

公开(公告)日：2007-11-06

申请号：US10627334

申请日：2003-07-24

申请人： Austin H. Lesea ,  Peter H. Alfke

发明人： Austin H. Lesea ,  Peter H. Alfke

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L23/532

CPC分类号： H01L23/5222 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： In an integrated circuit, a layer including a plurality of conductive wires is described. A first wire, having sidewalls, is tapered from a proximal end which has a first width to a distal end which has a second width, to reduce width from the first width to the second width, and the first wire also has a substantially vertical surface. A second wire, spaced apart from the first wire, also has a substantially vertical surface. The first wire and the second wire are each horizontally disposed along side each other forming a part of a sidewall capacitor between facing sidewalls. Capacitors are created between the first substantially vertical surface and the second substantially vertical surface, the capacitors are respectively associated with capacitances and with a plurality of loads, the plurality of loads is progressively reduced responsive to a progressive reduction of the capacitances as associated with the first wire taper.

摘要翻译： 在集成电路中，描述包括多根导线的层。 具有侧壁的第一线从具有第一宽度的第一宽度到具有第二宽度的远端的近端渐缩，以减小从第一宽度到第二宽度的宽度，并且第一线还具有基本垂直的表面 。 与第一线间隔开的第二线也具有基本垂直的表面。 第一线和第二线各自水平地彼此相对地设置，在相对的侧壁之间形成侧壁电容器的一部分。 电容器在第一基本上垂直的表面和第二基本上垂直的表面之间产生，电容器分别与电容和多个负载相关联，多个负载响应于与第一个相关联的电容的逐渐减小而逐渐减小 丝锥。

公开(公告)号：US06353341B1

公开(公告)日：2002-03-05

申请号：US09439844

申请日：1999-11-12

申请人： Austin H. Lesea ,  Peter H. Alfke ,  Jennifer Wong ,  Steven P. Young

发明人： Austin H. Lesea ,  Peter H. Alfke ,  Jennifer Wong ,  Steven P. Young

IPC分类号： G01R2902

CPC分类号： G01R31/31922 ,  G01R31/31937

摘要： A clock signal is monitored to detect a transition from a first logic state to a second logic state. Once this transition is detected, subsequent transitions of the clock signal are ignored for a predetermined time period during which signal interference is most significant. After lapse of the predetermined time period, the clock signal is again monitored to detect subsequent state transitions. In some embodiments, the clock signal is delayed using a delay circuit to produce a delayed clock signal which is used to force the clock signal to the second logic state for a predetermined time period. In one embodiment, the predetermined time period is user-selectable via one or more selectable taps on the delay circuit.

摘要翻译： 监视时钟信号以检测从第一逻辑状态到第二逻辑状态的转变。 一旦检测到该转变，则在时间信号的后续转换在信号干扰最显着的预定时间段期间被忽略。 在经过预定时间段之后，再次监视时钟信号以检测随后的状态转换。 在一些实施例中，使用延迟电路来延迟时钟信号以产生延迟的时钟信号，该延迟时钟信号用于将时钟信号强制到第二逻辑状态达预定时间段。 在一个实施例中，通过延迟电路上的一个或多个可选择的抽头，预定时间段是用户可选择的。

公开(公告)号：US07759801B1

公开(公告)日：2010-07-20

申请号：US11903016

申请日：2007-09-19

申请人： Austin H. Lesea ,  Peter H. Alfke

发明人： Austin H. Lesea ,  Peter H. Alfke

IPC分类号： H01L23/48

CPC分类号： H01L23/5222 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： A first wire having sidewalls of an integrated circuit is tapered from the proximal end to the distal end to reduce width from the first width to the second width. A second wire, spaced apart from the first wire, the second wire has sidewalls. The first wire and the second wire are each horizontally disposed along side each other forming a part of a sidewall capacitor between facing sidewalls. The sidewall capacitor capacitance is progressively reduced responsive to the first wire taper.

摘要翻译： 具有集成电路侧壁的第一线从近端到远端是渐缩的，以减小从第一宽度到第二宽度的宽度。 与第一线间隔开的第二线，第二线具有侧壁。 第一线和第二线各自水平地彼此相对地设置，在相对的侧壁之间形成侧壁电容器的一部分。 响应于第一线锥度，侧壁电容器电容逐渐减小。

公开(公告)号：US07619486B1

公开(公告)日：2009-11-17

申请号：US11715534

申请日：2007-03-07

申请人： Austin H. Lesea

发明人： Austin H. Lesea

IPC分类号： H03L1/04

CPC分类号： H03L1/022 ,  G01K7/346 ,  H03L1/026 ,  H03L7/18

摘要： An integrated circuit fabricated in a multiple oxide process can be used to provide a temperature-insensitive circuit. The temperature-insensitive circuit can be a ring oscillator; this ring oscillator can be used as a low-cost integrated reference frequency to monitor and to modify the behavior of the integrated to produce the desired results. In some embodiments, the reference oscillator output can be compared to second oscillator output where the second oscillator performance is temperature-sensitive. The comparison result can be monitored and processed to power down the integrated circuit.

摘要翻译： 可以使用以多重氧化物工艺制造的集成电路来提供温度不敏感的电路。 温度不敏感电路可以是环形振荡器; 该环形振荡器可以用作低成本的集成参考频率来监视和修改集成的行为以产生期望的结果。 在一些实施例中，可以将参考振荡器输出与第二振荡器输出进行比较，其中第二振荡器性能是温度敏感的。 可以对比较结果进行监控和处理，以使集成电路断电。

公开(公告)号：US07254157B1

公开(公告)日：2007-08-07

申请号：US10109130

申请日：2002-03-27

申请人： Patrick J. Crotty ,  Austin H. Lesea

发明人： Patrick J. Crotty ,  Austin H. Lesea

IPC分类号： H04B1/69 ,  H04B1/707 ,  H04B1/713

CPC分类号： H03K3/84

摘要： A method of and apparatus for generating a spread spectrum clock signal on an integrated circuit are provided. A target frequency generated by a ring oscillator can be modulated by varying a supply voltage to the ring oscillator, thereby changing the target frequency. In one embodiment, the supply voltage is generated by an analog multiplexer that can be digitally controlled. A fixed voltage source can provide an input signal to the analog multiplexer. In one embodiment, the fixed voltage source can be implemented with a unity gain amplifier.

摘要翻译： 提供了一种在集成电路上产生扩频时钟信号的方法和装置。 可以通过改变环形振荡器的电源电压来调制由环形振荡器产生的目标频率，从而改变目标频率。 在一个实施例中，电源电压由可被数字控制的模拟多路复用器产生。 固定电压源可以向模拟多路复用器提供输入信号。 在一个实施例中，固定电压源可以用单位增益放大器来实现。

公开(公告)号：US07240320B1

公开(公告)日：2007-07-03

申请号：US10989679

申请日：2004-11-16

申请人： Stephen M. Trimberger ,  Austin H. Lesea ,  Bernard J. New

发明人： Stephen M. Trimberger ,  Austin H. Lesea ,  Bernard J. New

IPC分类号： G06F17/50

CPC分类号： G06F17/5054

摘要： A method of implementing a design on a programmable logic device (PLD) includes generating a database that identifies correspondence between resources and programming frames of the PLD. A first PLD design is compiled, wherein the first design uses a first set of resources in a first manner. Costs associated with using the first set of resources of the first design in the first manner are reduced. A second PLD design is then compiled, applying the reduced costs associated with using the first set of resources. A second set of resources required to compile the second design is identified, wherein the second set of resources is not used in the same manner as the first set of resources. A set of programming frames associated with the second set of resources is identified. Costs associated with using a third set of resources associated with the set of programming frames are increased.

摘要翻译： 在可编程逻辑器件（PLD）上实现设计的方法包括生成识别PLD的资源和编程帧之间的对应关系的数据库。 编译第一PLD设计，其​​中第一设计以第一方式使用第一组资源。 降低了以第一种方式使用第一种设计的第一组资源相关联的成本。 然后编制第二PLD设计，应用与使用第一组资源相关联的降低的成本。 识别编译第二设计所需的第二组资源，其中第二组资源不以与第一组资源相同的方式使用。 识别与第二组资源相关联的一组编程帧。 与使用与该组编程帧相关联的第三组资源相关联的成本增加。

公开(公告)号：US07062692B1

公开(公告)日：2006-06-13

申请号：US10255502

申请日：2002-09-26

申请人： Austin H. Lesea

发明人： Austin H. Lesea

IPC分类号： G01R31/28

CPC分类号： G01R31/31725 ,  G01R31/31726

摘要： Method and apparatus are described for duty cycle determination and adjustment. More particularly, an output signal is sampled and provided to duty cycle check circuitry which characterizes the duty cycle of the sampled output signal. This characterization may be provided to a wafer prober or integrated circuit tester to determine whether duty cycle is within an acceptance range. Alternatively, the duty cycle indicator signal may be provided to drive adjustment circuitry. In response to duty cycle not being within an acceptance range, drive adjust circuitry provides a drive adjustment signal to adjust duty cycle at an output buffer by turning on one or more p-channel drive transistors, one or more n-channel drive transistors, or a combination of both. Moreover, wells may be biased responsive to a detected duty cycle in order to correct the duty cycle.

摘要翻译： 描述了用于占空比确定和调整的方法和装置。 更具体地，输出信号被采样并提供给表征采样输出信号的占空比的占空比检查电路。 该表征可以提供给晶片探测器或集成电路测试器，以确定占空比是否在接受范围内。 或者，占空比指示信号可以被提供给驱动调整电路。 响应于占空比不在允许范围内，驱动调节电路提供驱动调节信号，以通过接通一个或多个p沟道驱动晶体管，一个或多个n沟道驱动晶体管或 两者的结合。 此外，孔可以响应于检测到的占空比而被偏置，以便校正占空比。

公开(公告)号：US06849951B1

公开(公告)日：2005-02-01

申请号：US10377863

申请日：2003-02-28

申请人： Stephen M. Trimberger ,  Austin H. Lesea

发明人： Stephen M. Trimberger ,  Austin H. Lesea

IPC分类号： H01L23/528 ,  H01L23/64 ,  H01L25/065 ,  H01L23/52

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L23/5286 ,  H01L23/642 ,  H01L24/48 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/12036 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/16152 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A die having a bypass capacitor is stacked on another die having an active circuit. The active circuit draws a spike of current, for example, during a switching period of a voltage on its output lead from one digital logic level to another digital logic level. The bypass capacitor provides a portion of the spike of current through a conductive plug that extends from a plate of the bypass capacitor to a power lead of the active circuit. The length of the conductive plug is reduced by extending the conductive plug from the bypass capacitor to the active circuit orthogonally to the planar orientation of the dice. Reducing the length of the conductive plug reduces the resistance and inductance of the conductive plug and, in turn, reduces the drop in voltage between the voltage on the bypass capacitor and the voltage on the power lead of the active circuit.

摘要翻译： 具有旁路电容器的管芯堆叠在具有有源电路的另一管芯上。 有源电路例如在其输出引线上的电压从一个数字逻辑电平到另一数字逻辑电平的开关周期期间画出电流尖峰。 旁路电容器通过从旁路电容器的板延伸到有源电路的电源线的导电插头提供电流尖峰的一部分。 通过将导电插塞从旁路电容器延伸到与裸片的平面取向正交的有源电路，导电插头的长度减小。 降低导电插头的长度会降低导电插头的电阻和电感，进而降低旁路电容器上的电压与有源电路的电源线上的电压之间的电压降。

公开(公告)号：US06735110B1

公开(公告)日：2004-05-11

申请号：US10125666

申请日：2002-04-17

申请人： Austin H. Lesea

发明人： Austin H. Lesea

IPC分类号： G11C1100

CPC分类号： G11C11/4125

摘要： Method and apparatus are described for providing memory cells enhanced for resistance to single event upsets. In one embodiment, transistors are coupled between cross coupled inverters of a latch, thus in a small area providing both single-event-upset resistivity most of the time, and high speed during writing to the memory cell. Alternatively, inductors coupled between inverters of a latch may be used.

公开(公告)号：US06445238B1

公开(公告)日：2002-09-03

申请号：US09452234

申请日：1999-12-01

申请人： Austin H. Lesea

发明人： Austin H. Lesea

IPC分类号： H03H1126

CPC分类号： H03H11/265 ,  H03K2005/00143

摘要： The supply voltage to which a delay circuit's buffer stages are coupled is adjusted in response to changes in temperature according to a predetermined relationship to maintain a substantially constant buffer stage gate delay over temperature variations. Decreasing gate delays resulting from decreases in temperature are offset by decreasing the supply voltage, which in turn increases gate delays. Conversely, increasing gate delays resulting from increases in temperature are offset by increasing the supply voltage, which in turn decreases gate delays. In some embodiments, a control circuit is connected to the reference voltage circuit that supplies VCC to the delay circuit, and adjusts VCC in response to temperature to maintain substantially constant gate delay over temperature. In one embodiment, the control circuit includes a microprocessor and a look-up table containing desired supply voltage versus temperature mappings. In another embodiment, the control circuit is formed as part of an existing bandgap reference circuit associated with the reference voltage circuit, and therefore consumes minimal silicon area.

摘要翻译： 响应于根据预定关系的温度变化来调节延迟电路的缓冲级耦合到的电源电压，以保持在温度变化上基本恒定的缓冲级门延迟。 通过降低电源电压来抵消由温度降低导致的门延迟的降低，这进而增加了门延迟。 相反，由于温度升高引起的栅极延迟增加可通过增加电源电压来抵消，这进而降低了栅极延迟。 在一些实施例中，控制电路连接到将VCC提供给延迟电路的参考电压电路，并且响应于温度来调节VCC以在温度上保持基本恒定的门延迟。 在一个实施例中，控制电路包括微处理器和包含期望的电源电压对温度映射的查找表。 在另一个实施例中，控制电路形成为与参考电压电路相关联的现有带隙参考电路的一部分，因此消耗最小的硅面积。