公开(公告)号：US09129856B2

公开(公告)日：2015-09-08

申请号：US13179248

申请日：2011-07-08

申请人： Wei Xia ,  Xiangdong Chen

发明人： Wei Xia ,  Xiangdong Chen

IPC分类号： H01L27/115 ,  H01L21/8238

CPC分类号： H01L27/11534 ,  H01L21/823842

摘要： According to one exemplary embodiment, a method for concurrently fabricating a memory region with a logic region in a common substrate includes forming a lower dielectric segment in the common substrate in the memory and logic regions. The method also includes forming a polysilicon segment over the lower dielectric segment in the memory region, while concurrently forming a sacrificial polysilicon segment over the lower dielectric segment in the logic region. Furthermore, the method includes removing from the logic region the lower dielectric segment and the sacrificial polysilicon segment. The method additionally includes forming a high-k segment in the logic region over the common substrate, and in the memory region over the polysilicon segment and forming a metal segment over the high-k segment in the logic and memory regions. An exemplary structure achieved by the described exemplary method is also disclosed.

摘要翻译： 根据一个示例性实施例，用于同时制造具有公共衬底中的逻辑区域的存储区域的方法包括在存储器和逻辑区域中的公共衬底中形成下部介电段。 该方法还包括在存储器区域中的下介电段上形成多晶硅段，同时在逻辑区域中的下介电段上同时形成牺牲多晶硅段。 此外，该方法包括从逻辑区域去除下介电段和牺牲多晶硅段。 该方法还包括在公共衬底上的逻辑区域中形成高k区段，并在多晶硅区段上的存储区域中形成高k区段，并在逻辑和存储区域中的高k区段上形成金属区段。 还公开了通过描述的示例性方法实现的示例性结构。

公开(公告)号：US08748277B2

公开(公告)日：2014-06-10

申请号：US13613520

申请日：2012-09-13

申请人： Xiangdong Chen ,  Wei Xia ,  Henry Kuo-Shun Chen

发明人： Xiangdong Chen ,  Wei Xia ,  Henry Kuo-Shun Chen

IPC分类号： H01L21/336

CPC分类号： H01L29/0878 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

摘要： According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.

摘要翻译： 根据示例性实施例，用于制造诸如LDMOS晶体管的MOS晶体管的方法包括在栅极的第一侧壁下面的第一阱中形成自对准的轻掺杂区域。 该方法还包括在栅极的第二侧壁下方形成自对准延伸区域，其中自对准延伸区域从第二阱延伸到第一阱中。 该方法还包括形成与栅极的第二侧壁间隔开的漏极区域。 该方法还包括在自对准轻掺杂区域和第一阱中形成源极区域。 自对准轻掺杂区域和自对准延伸区域限定诸如LDMOS晶体管的MOS晶体管的沟道长度。

公开(公告)号：US08716831B2

公开(公告)日：2014-05-06

申请号：US13249022

申请日：2011-09-29

申请人： Xiangdong Chen ,  Wei Xia

发明人： Xiangdong Chen ,  Wei Xia

IPC分类号： H01L23/525

CPC分类号： H01L23/5256 ,  H01L27/0629 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/00

摘要： An eFuse structure having a first metal layer serving as a fuse with a gate including an undoped polysilicon (poly), a second metal layer and a high-K dielectric layer all formed on a silicon substrate with a Shallow Trench Isolation formation, and a process of fabricating same are provided. The eFuse structure enables use of low amounts of current to blow a fuse thus allowing the use of a smaller MOSFET.

摘要翻译： 一种eFuse结构，其具有用作具有栅极的第一金属层，所述栅极包括未经掺杂的多晶硅（poly），第二金属层和高K电介质层，所述第一金属层全部用浅沟槽隔离层形成在硅衬底上，以及工艺 提供制造相同的。 eFuse结构使得能够使用少量的电流来熔断熔丝，从而允许使用更小的MOSFET。

公开(公告)号：US08558300B2

公开(公告)日：2013-10-15

申请号：US12590370

申请日：2009-11-06

申请人： Wei Xia ,  Xiangdong Chen ,  Frank Hui

发明人： Wei Xia ,  Xiangdong Chen ,  Frank Hui

IPC分类号： H01L29/788

CPC分类号： H01L21/28273 ,  H01L27/11526 ,  H01L27/11546

摘要： According to one exemplary embodiment, a method for fabricating a flash memory cell in a semiconductor die includes forming a control gate stack overlying a floating gate stack in a memory region of a substrate, where the floating gate stack includes a floating gate overlying a portion of a dielectric one layer. The floating gate includes a portion of a metal one layer and the dielectric one layer includes a first high-k dielectric material. The control gate stack can include a control gate including a portion of a metal two layer, where the metal one layer can include a different metal than the metal two layer.

摘要翻译： 根据一个示例性实施例，一种用于在半导体管芯中制造快闪存储器单元的方法包括：在衬底的存储器区域中形成覆盖浮置栅极堆叠的控制栅极堆叠，其中浮置栅极堆叠包括覆盖一部分 电介质层。 浮栅包括金属一层的一部分，电介质一层包括第一高k电介质材料。 控制栅极堆叠可以包括包括金属两层的一部分的控制栅极，其中金属一层可以包括与金属两层不同的金属。

公开(公告)号：US20130099317A1

公开(公告)日：2013-04-25

申请号：US13277547

申请日：2011-10-20

申请人： Wei Xia ,  Xiangdong Chen

发明人： Wei Xia ,  Xiangdong Chen

IPC分类号： H01L27/12

CPC分类号： H01L29/785 ,  H01L2029/7857

摘要： According to one exemplary embodiment, a fin-based adjustable resistor includes a fin channel of a first conductivity type, and a gate surrounding the fin channel. The fin-based adjustable resistor also includes first and second terminals of the first conductivity type being contiguous with the fin channel, and being situated on opposite sides of the fin channel. The fin channel is lower doped relative to the first and second terminals. The resistance of the fin channel between the first and second terminals is adjusted by varying a voltage applied to the gate so as to achieve the fin-based adjustable resistor. The gate can be on at least two sides of the fin channel. Upon application of a depletion voltage, the fin channel can be depleted before an inversion is formed in the fin channel.

摘要翻译： 根据一个示例性实施例，鳍状可调电阻器包括第一导电类型的鳍状沟道和围绕鳍状沟道的栅极。 鳍状可调电阻器还包括第一导电类型的第一和第二端子，其与鳍状通道邻接并位于翅片通道的相对侧上。 翅片通道相对于第一和第二端子较低掺杂。 通过改变施加到栅极的电压来调节第一和第二端子之间的鳍状通道的电阻，从而实现基于鳍片的可调电阻器。 门可以在鳍通道的至少两侧。 在施加耗尽电压时，在鳍式通道中形成反转之前，可以耗尽鳍通道。

公开(公告)号：US20130017658A1

公开(公告)日：2013-01-17

申请号：US13613520

申请日：2012-09-13

申请人： Xiangdong Chen ,  Wei Xia ,  Henry Kuo-Shun Chen

发明人： Xiangdong Chen ,  Wei Xia ,  Henry Kuo-Shun Chen

IPC分类号： H01L21/336

CPC分类号： H01L29/0878 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

摘要： According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.

摘要翻译： 根据示例性实施例，用于制造诸如LDMOS晶体管的MOS晶体管的方法包括在栅极的第一侧壁下面的第一阱中形成自对准的轻掺杂区域。 该方法还包括在栅极的第二侧壁下方形成自对准延伸区域，其中自对准延伸区域从第二阱延伸到第一阱中。 该方法还包括形成与栅极的第二侧壁间隔开的漏极区域。 该方法还包括在自对准轻掺杂区域和第一阱中形成源极区域。 自对准轻掺杂区域和自对准延伸区域限定诸如LDMOS晶体管的MOS晶体管的沟道长度。

公开(公告)号：US20110210384A1

公开(公告)日：2011-09-01

申请号：US12660619

申请日：2010-03-01

申请人： Wei Xia ,  Xiangdong Chen

发明人： Wei Xia ,  Xiangdong Chen

IPC分类号： H01L27/06 ,  H01L21/02 ,  H01L21/8234

CPC分类号： H01L27/0629 ,  H01L23/5223 ,  H01L27/0805 ,  H01L27/0811 ,  H01L27/092 ,  H01L28/60 ,  H01L28/65 ,  H01L29/4232 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a scalable integrated MIM capacitor in a semiconductor die includes a high-k dielectric segment over a substrate and a metal segment over the high-k dielectric segment, where the metal segment forms a capacitor terminal of the integrated MIM capacitor. The capacitor further includes a filler laterally separating consecutive capacitor terminals, where the filler can be used as a capacitor dielectric of the integrated MIM capacitor. In one embodiment, the metal segment comprises a gate metal. In another embodiment, the integrated MIM capacitor is formed substantially concurrently with one or more transistors without requiring additional fabrication process steps.

摘要翻译： 根据一个实施例，半导体管芯中的可扩展集成MIM电容器包括衬底上的高k电介质段和高k电介质段上的金属段，其中金属段形成集成MIM电容器的电容器端子。 电容器还包括横向分离连续的电容器端子的填料，其中填料可以用作集成MIM电容器的电容器电介质。 在一个实施例中，金属段包括栅极金属。 在另一个实施例中，集成MIM电容器基本上与一个或多个晶体管同时形成，而不需要额外的制造工艺步骤。

公开(公告)号：US20110031585A1

公开(公告)日：2011-02-10

申请号：US12462692

申请日：2009-08-07

申请人： Wei Xia ,  Xiangdong Chen ,  Akira Ito

发明人： Wei Xia ,  Xiangdong Chen ,  Akira Ito

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L27/0629 ,  H01L28/60

摘要： According to one exemplary embodiment, a method for fabricating a MIM capacitor in a semiconductor die includes forming a dielectric one segment over a substrate and a metal one segment over the dielectric one segment, where the metal one segment forms a lower electrode of the MIM capacitor. The method further includes forming a dielectric two segment over the dielectric one segment and a metal two segment over the dielectric two segment, where a portion of the metal two segment forms an upper electrode of the MIM capacitor. The metal one segment comprises a first gate metal. The metal two segment can comprise a second gate metal.

摘要翻译： 根据一个示例性实施例，一种用于在半导体管芯中制造MIM电容器的方法包括在电介质一段上形成电介质一段并在电介质一段上形成金属一段，其中金属一段形成MIM电容器的下电极 。 该方法还包括在电介质一段上形成电介质两段，在电介质两段上形成金属二段，其中金属二段的一部分形成MIM电容器的上电极。 金属一段包括第一栅极金属。 金属二段可以包括第二栅极金属。

公开(公告)号：US20100320561A1

公开(公告)日：2010-12-23

申请号：US12456833

申请日：2009-06-22

申请人： Wei Xia ,  Xiangdong Chen ,  Akira Ito

发明人： Wei Xia ,  Xiangdong Chen ,  Akira Ito

IPC分类号： H01L23/525 ,  H01L21/768

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one exemplary embodiment, a method for forming a one-time programmable metal fuse structure includes forming a metal fuse structure over a substrate, the metal fuse structure including a gate metal segment situated between a dielectric segment and a polysilicon segment, a gate metal fuse being formed in a portion of the gate metal segment. The method further includes doping the polysilicon segment so as to form first and second doped polysilicon portions separated by an undoped polysilicon portion where, in one embodiment, the gate metal fuse is substantially co-extensive with the undoped polysilicon portion. The method can further include forming a first silicide segment on the first doped polysilicon portion and a second silicide segment on the second doped polysilicon portion, where the first and second silicide segments form respective terminals of the one-time programmable metal fuse structure.

摘要翻译： 根据一个示例性实施例，一种用于形成一次性可编程金属熔丝结构的方法包括在衬底上形成金属熔丝结构，所述金属熔丝结构包括位于介电段和多晶硅段之间的栅极金属段，栅极金属 熔丝形成在栅极金属段的一部分中。 该方法还包括掺杂多晶硅段以便形成由未掺杂多晶硅部分分开的第一和第二掺杂多晶硅部分，其中在一个实施例中，栅极金属熔丝与未掺杂的多晶硅部分基本上共同延伸。 该方法还可以包括在第一掺杂多晶硅部分上形成第一硅化物部分和在第二掺杂多晶硅部分上形成第二硅化物部分，其中第一和第二硅化物部分形成一次性可编程金属熔丝结构的相应端子。

公开(公告)号：US09082751B2

公开(公告)日：2015-07-14

申请号：US13232737

申请日：2011-09-14

申请人： Xiangdong Chen ,  Wei Xia

发明人： Xiangdong Chen ,  Wei Xia

IPC分类号： H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L29/4236 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/66659 ,  H01L29/66787 ,  H01L29/7835 ,  H01L29/785

摘要： According to one embodiment, a half-FinFET semiconductor device comprises a gate structure formed over a semiconductor body. The semiconductor body includes a source region comprised of a plurality of fins extending beyond a first side of the gate structure and a continuous drain region adjacent a second side of the gate structure opposite the plurality of fins. The continuous drain region causes the half-FinFET semiconductor device to have a reduced ON-resistance. A method for fabricating a semiconductor device having a half-FinFET structure comprises designating source and drain regions in a semiconductor body, etching the source region to produce a plurality of source fins while masking the drain region during the etching to provide a continuous drain region, thereby resulting in the half-FinFET structure having a reduced ON-resistance.

摘要翻译： 根据一个实施例，半FinFET半导体器件包括形成在半导体本体上的栅极结构。 半导体本体包括源极区域，该区域包括延伸超过栅极结构的第一侧面的多个鳍片，以及与栅极结构的与多个鳍片相对的第二侧相邻的连续漏极区域。 连续漏极区域使得半FinFET半导体器件具有降低的导通电阻。 一种制造具有半FinFET结构的半导体器件的方法包括：在半导体本体中指定源极和漏极区域，蚀刻源极区域以产生多个源极鳍片，同时在蚀刻期间掩蔽漏极区域以提供连续的漏极区域， 从而导致半FinFET结构具有降低的导通电阻。