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    Partial swing low power CMOS logic circuits
    3.
    发明授权
    Partial swing low power CMOS logic circuits 有权
    部分摆幅低功耗CMOS逻辑电路

    公开(公告)号：US06621305B2

    公开(公告)日：2003-09-16

    申请号：US09920886

    申请日：2001-08-03

    申请人： Osamu Samuel Nakagawa ,  Norman Chang ,  Shen Lin ,  Weize Xie ,  Kenynmyung Lee

    发明人： Osamu Samuel Nakagawa ,  Norman Chang ,  Shen Lin ,  Weize Xie ,  Kenynmyung Lee

    IPC分类号： H03K19096

    CPC分类号： H03K19/0963

    摘要： A logic gate circuit and related methods and apparatus exhibit reduced voltage swing and thereby consume less power. The circuit is connected to a plurality of input signals and a clock signal. The circuit produces an output. The circuit comprises a node, a pull-down network and an N-type MOS transistor. The pull-down network is connected to the node, a first reference voltage, the plurality of inputs and the clock signal. The N-type MOS transistor is connected between the node and a second reference voltage. The N-type MOS transistor is also connected to a complement of the clock signal. A method of the invention accepts a complement of a clock signal and pre-charges a node to a voltage less than a power supply voltage, in response to the complement of the clock signal. The method also accepts a plurality of input signals and accepts the clock signal. The method conditionally discharges the node, in response to the clock signal, on the basis of the plurality of input signals.

    摘要翻译： 逻辑门电路和相关方法和装置显示出降低的电压摆幅，从而消耗更少的功率。 电路连接到多个输入信号和时钟信号。 电路产生输出。 该电路包括一个节点，一个下拉网络和一个N型MOS晶体管。 下拉网络连接到节点，第一参考电压，多个输入和时钟信号。 N型MOS晶体管连接在节点和第二参考电压之间。 N型MOS晶体管也连接到时钟信号的补码。 响应于时钟信号的补码，本发明的方法接受时钟信号的补码并且将节点预充电到小于电源电压的电压。 该方法还接受多个输入信号并接受时钟信号。 该方法响应于时钟信号，有选择地根据多个输入信号对节点进行放电。

    System for improving circuit simulations by utilizing a simplified circuit model based on effective capacitance and inductance values
    4.
    发明授权
    System for improving circuit simulations by utilizing a simplified circuit model based on effective capacitance and inductance values 有权
    通过利用基于有效电容和电感值的简化电路模型来改善电路模拟的系统

    公开(公告)号：US06567960B2

    公开(公告)日：2003-05-20

    申请号：US09972052

    申请日：2001-10-09

    申请人： Norman Chang ,  Yu Cao ,  Osamu Samuel Nakagawa ,  Shen Lin ,  Weize Xie

    发明人： Norman Chang ,  Yu Cao ,  Osamu Samuel Nakagawa ,  Shen Lin ,  Weize Xie

    IPC分类号： G06F1750

    CPC分类号： G06F17/5036

    摘要： An RLC module is configured to provide a simplified circuit modeling of a selected circuit net (or portion) of an electronic circuit. The RLC module may be configured to substitute an RLC circuit model for the selected circuit net, where the effective values of the capacitance and inductance for the RLC circuit model are retrieved from a table of capacitance and inductance values. A set of interconnect geometry factors (e.g., line length, line width, driver/receiver length, etc.) that describes the circuit net is used as an index into the table of capacitance and inductance values. The retrieved values of the effective capacitance and inductances values may be used to calculate a delay for the RLC circuit model. The RLC module may provide the capability to quickly calculate a delay for a selected circuit net without using computationally intensive calculations for inductance and capacitance values of circuit nets.

    摘要翻译： RLC模块被配置为提供电子电路的所选电路网（或部分）的简化电路建模。 RLC模块可以被配置为将RLC电路模型替换为所选择的电路网，其中从电容和电感值的表中检索RLC电路模型的电容和电感的有效值。 使用描述电路网的一组互连几何因素（例如，线路长度，线宽度，驱动器/接收机长度等）作为电容和电感值表的索引。 可以使用有效电容和电感值的检索值来计算RLC电路模型的延迟。 RLC模块可以提供快速计算所选择的电路网的延迟的能力，而不用对电路网的电感和电容值进行计算密集的计算。

    Ramp loading circuit for reducing current surges
    5.
    发明授权
    Ramp loading circuit for reducing current surges 失效
    用于减小电流浪涌的斜坡加载电路

    公开(公告)号：US06462607B1

    公开(公告)日：2002-10-08

    申请号：US09995640

    申请日：2001-11-29

    申请人： Osamu Samuel Nakagawa

    发明人： Osamu Samuel Nakagawa

    IPC分类号： G05F100

    CPC分类号： H03K17/16 ,  H03K4/00

    摘要： A ramp loading circuit for slowing current change in a circuit block. The circuit may include a plurality of load circuits placed in parallel with the circuit block and a control circuit. Each load circuit may provide a path for current flow when the load circuit is activated. Each load circuit may also be configured to allow a gradual decrease in current flow through the path when the load circuit is deactivated. The control circuit may be configured to deactivate each load circuit before the circuit block enters the sleep mode.

    摘要翻译： 斜坡加载电路，用于减缓电路块中的电流变化。 电路可以包括与电路块并联放置的多个负载电路和控制电路。 当负载电路被激活时，每个负载电路可以提供用于电流的路径。 每个负载电路还可以被配置为当负载电路被去激活时允许通过路径的电流的逐渐减小。 控制电路可以被配置为在电路块进入睡眠模式之前停用每个负载电路。