公开(公告)号：US06567960B2

公开(公告)日：2003-05-20

申请号：US09972052

申请日：2001-10-09

申请人： Norman Chang ,  Yu Cao ,  Osamu Samuel Nakagawa ,  Shen Lin ,  Weize Xie

发明人： Norman Chang ,  Yu Cao ,  Osamu Samuel Nakagawa ,  Shen Lin ,  Weize Xie

IPC分类号： G06F1750

CPC分类号： G06F17/5036

摘要： An RLC module is configured to provide a simplified circuit modeling of a selected circuit net (or portion) of an electronic circuit. The RLC module may be configured to substitute an RLC circuit model for the selected circuit net, where the effective values of the capacitance and inductance for the RLC circuit model are retrieved from a table of capacitance and inductance values. A set of interconnect geometry factors (e.g., line length, line width, driver/receiver length, etc.) that describes the circuit net is used as an index into the table of capacitance and inductance values. The retrieved values of the effective capacitance and inductances values may be used to calculate a delay for the RLC circuit model. The RLC module may provide the capability to quickly calculate a delay for a selected circuit net without using computationally intensive calculations for inductance and capacitance values of circuit nets.

摘要翻译： RLC模块被配置为提供电子电路的所选电路网（或部分）的简化电路建模。 RLC模块可以被配置为将RLC电路模型替换为所选择的电路网，其中从电容和电感值的表中检索RLC电路模型的电容和电感的有效值。 使用描述电路网的一组互连几何因素（例如，线路长度，线宽度，驱动器/接收机长度等）作为电容和电感值表的索引。 可以使用有效电容和电感值的检索值来计算RLC电路模型的延迟。 RLC模块可以提供快速计算所选择的电路网的延迟的能力，而不用对电路网的电感和电容值进行计算密集的计算。

公开(公告)号：US06661281B2

公开(公告)日：2003-12-09

申请号：US09995639

申请日：2001-11-29

申请人： Osamu Samuel Nakagawa ,  Norman Chang ,  Shen Lin ,  Weize Xie ,  Xuejue Huang

发明人： Osamu Samuel Nakagawa ,  Norman Chang ,  Shen Lin ,  Weize Xie ,  Xuejue Huang

IPC分类号： H03B100

CPC分类号： H02H9/001 ,  H03K17/16 ,  Y10T307/469

摘要： A method reduces noise resulting from a current surge in a circuit. A plurality of loading elements, parallel with the circuit being protected, are connected sequentially and disconnected. The connection of the loading elements results in a ramping up of current through the circuit without a sudden surge. In a preferred embodiment, an apparatus for slowing a current change in a circuit is described. The apparatus comprises a plurality of loading elements placed in parallel with the circuit, each of the elements providing a path for current flow, and a control circuit for selectively opening or closing at least one of said paths to prevent or enable current flow through the at least one of the paths.

公开(公告)号：US06981231B2

公开(公告)日：2005-12-27

申请号：US10079508

申请日：2002-02-22

申请人： Weize Xie ,  Norman Chang ,  Shen Lin ,  Osamu Samuel Nakagawa

发明人： Weize Xie ,  Norman Chang ,  Shen Lin ,  Osamu Samuel Nakagawa

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A system and method to reduce leakage power consumption of electronic devices. In addition to assigning threshold voltages, sizes of the transistors within the device may be varied to provide a range of options to meet the timing requirements while minimizing the leakage power consumption.

摘要翻译： 一种降低电子设备泄漏功耗的系统和方法。 除了分配阈值电压之外，器件内的晶体管的尺寸可以改变以提供一系列选项以满足定时要求，同时最小化泄漏功率消耗。

公开(公告)号：US06621305B2

公开(公告)日：2003-09-16

申请号：US09920886

申请日：2001-08-03

申请人： Osamu Samuel Nakagawa ,  Norman Chang ,  Shen Lin ,  Weize Xie ,  Kenynmyung Lee

发明人： Osamu Samuel Nakagawa ,  Norman Chang ,  Shen Lin ,  Weize Xie ,  Kenynmyung Lee

IPC分类号： H03K19096

CPC分类号： H03K19/0963

摘要： A logic gate circuit and related methods and apparatus exhibit reduced voltage swing and thereby consume less power. The circuit is connected to a plurality of input signals and a clock signal. The circuit produces an output. The circuit comprises a node, a pull-down network and an N-type MOS transistor. The pull-down network is connected to the node, a first reference voltage, the plurality of inputs and the clock signal. The N-type MOS transistor is connected between the node and a second reference voltage. The N-type MOS transistor is also connected to a complement of the clock signal. A method of the invention accepts a complement of a clock signal and pre-charges a node to a voltage less than a power supply voltage, in response to the complement of the clock signal. The method also accepts a plurality of input signals and accepts the clock signal. The method conditionally discharges the node, in response to the clock signal, on the basis of the plurality of input signals.

摘要翻译： 逻辑门电路和相关方法和装置显示出降低的电压摆幅，从而消耗更少的功率。 电路连接到多个输入信号和时钟信号。 电路产生输出。 该电路包括一个节点，一个下拉网络和一个N型MOS晶体管。 下拉网络连接到节点，第一参考电压，多个输入和时钟信号。 N型MOS晶体管连接在节点和第二参考电压之间。 N型MOS晶体管也连接到时钟信号的补码。 响应于时钟信号的补码，本发明的方法接受时钟信号的补码并且将节点预充电到小于电源电压的电压。 该方法还接受多个输入信号并接受时钟信号。 该方法响应于时钟信号，有选择地根据多个输入信号对节点进行放电。

公开(公告)号：US06925555B2

公开(公告)日：2005-08-02

申请号：US09915531

申请日：2001-07-27

申请人： Norman Chang ,  Shen Lin ,  Osamu Nakagawa ,  Weize Xie

发明人： Norman Chang ,  Shen Lin ,  Osamu Nakagawa ,  Weize Xie

IPC分类号： G06F1/10 ,  G06F17/50 ,  G06F9/00 ,  G06F9/24

CPC分类号： G06F17/5045 ,  G06F1/10

摘要： A method determines a plurality of clock delay values. Each delay value is associated with a delay element on a clock line leading to a clock sink in a synchronous circuit. The method determines an initial set of delay values and executes an optimization algorithm, beginning with the initial set of delay values, to arrive at a set of delay values that at least approximately meets an criteria while satisfying timing constraints associated with selected pairs of logically connected clock sinks. In a preferred form, the optimization algorithm is a genetic algorithm or a gradient descent algorithm. The genetic algorithm involves selecting parent sets of delay values, crossing over so as to produce a child set of delay values, mutating the child set of delay values, evaluating how well the child set of delay values meets the criteria, and conditionally discarding the child set on the basis of the evaluating step. The gradient descent algorithm involves perturbing the initial set of delay values, evaluating how well the perturbed set of delay values meets the criteria, and conditionally discarding the perturbed set on the basis of the evaluating step. If the perturbed set is not discarded, then the gradient descent algorithm adjusts the values of the perturbed set in the same direction relative to the corresponding values in the initial set.

摘要翻译： 一种方法确定多个时钟延迟值。 每个延迟值与在同步电路中通向时钟信号的时钟线上的延迟元件相关联。 该方法确定初始的一组延迟值，并且执行从初始的延迟值开始的优化算法，以获得至少近似满足标准的一组延迟值，同时满足与选定的逻辑连接对相关联的定时约束 时钟汇 在优选形式中，优化算法是遗传算法或梯度下降算法。 遗传算法涉及选择父组的延迟值，跨越以产生子集延迟值，突变子集延迟值，评估子集延迟值如何满足标准，并有条件地丢弃小孩 在评估步骤的基础上设定。 梯度下降算法涉及扰乱初始的延迟值集合，评估扰动的延迟值集合满足准则的程度，以及基于评估步骤有条件地丢弃扰动集合。 如果扰动的集合不被丢弃，则梯度下降算法相对于初始集合中的对应值来调整扰动集合在相同方向上的值。

公开(公告)号：US06566924B2

公开(公告)日：2003-05-20

申请号：US09911398

申请日：2001-07-25

申请人： Shen Lin ,  Norman Chang ,  Keunmyung Lee ,  Osamu Nakagawa ,  Weize Xie

发明人： Shen Lin ,  Norman Chang ,  Keunmyung Lee ,  Osamu Nakagawa ,  Weize Xie

IPC分类号： H03L700

CPC分类号： H03L7/00 ,  G06F1/10

摘要： A system and method is provided for controlling clock skew to meet timing constraints for a semiconductor integrated circuit. On-chip self-tuning circuits can be connected to each latch in the integrated circuit for controlling clock skew. Each self-tuning circuit delays a clock signal that is input to a latch when the clock skew does not satisfy the timing constraint for that latch. The self-tuning circuit repeatedly delays the clock signal until the clock skew is satisfied or until the delay becomes greater than or equal to a predetermined threshold. The delayed clock signal is then pushed to other latches in the integrated circuit until all the timing constraints for the integrated circuit are satisfied.

公开(公告)号：US06981230B1

公开(公告)日：2005-12-27

申请号：US10209081

申请日：2002-07-30

申请人： Shen Lin ,  Norman Chang ,  Weize Xie ,  Richard Chou

发明人： Shen Lin ,  Norman Chang ,  Weize Xie ,  Richard Chou

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F2217/78

摘要： An efficient inductance modeling approach for on-chip power-ground wires using their effective self-loop-inductances is disclosed. Instead of extracting the inductive coupling between every two parallel wires and putting this huge number inductance elements into circuit simulation, this technique determines the effective self-loop-inductance for each power or ground wire segment and only generates a circuit with these effective self-inductors for simulation. This approach greatly reduces the circuit size and makes the full-chip power-ground simulation with the consideration of inductance feasible.

摘要翻译： 公开了一种使用其有效自回路电感的片上电源线的高效电感建模方法。 不用提取每两根平行线之间的电感耦合，并将这么大数量的电感元件放入电路仿真中，这种技术决定了每个电源或接地线段的有效自环电感，并且只产生一个具有这些有效自感器的电路 用于模拟。 这种方法大大降低了电路尺寸，并且考虑到电感可以实现全芯片功率 - 地面仿真。