公开(公告)号：US07135783B2

公开(公告)日：2006-11-14

申请号：US10923585

申请日：2004-08-20

申请人： Wen-Kuei Hsieh ,  Hui-Min Mao ,  Yi-Nan Chen

发明人： Wen-Kuei Hsieh ,  Hui-Min Mao ,  Yi-Nan Chen

IPC分类号： H01L23/544 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L23/544 ,  H01L21/31144 ,  H01L21/76802 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming contact holes using a partially recessed hard mask. A substrate with a device region and an alignment region having an opening therein, acting as an alignment mark, is provided. A dielectric layer is formed overlying the substrate and fills the opening. A polysilicon layer is formed on the dielectric layer, with over the opening on the alignment region comprising a recessed region and on the device region comprising a plurality of holes therein to expose the underlying dielectric layer. The exposed dielectric layer on the device region is etched to form contact holes therein.

摘要翻译： 使用部分凹入的硬掩模形成接触孔的方法。 提供具有装置区域和其中具有开口的对准区域的基板，用作对准标记。 形成覆盖在基板上并填充开口的电介质层。 在电介质层上形成多晶硅层，其中对准区域上的开口包括凹陷区域，并且在其上包括多个孔的器件区域上露出下面的介电层。 蚀刻器件区域上的暴露的电介质层以在其中形成接触孔。

公开(公告)号：US20050275111A1

公开(公告)日：2005-12-15

申请号：US10923585

申请日：2004-08-20

申请人： Wen-Kuei Hsieh ,  Hui-Min Mao ,  Yi-Nan Chen

发明人： Wen-Kuei Hsieh ,  Hui-Min Mao ,  Yi-Nan Chen

IPC分类号： H01L21/027 ,  H01L21/311 ,  H01L21/768 ,  H01L23/48 ,  H01L23/485 ,  H01L23/544

CPC分类号： H01L23/544 ,  H01L21/31144 ,  H01L21/76802 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming contact holes using a partially recessed hard mask. A substrate with a device region and an alignment region having an opening therein, acting as an alignment mark, is provided. A dielectric layer is formed overlying the substrate and fills the opening. A polysilicon layer is formed on the dielectric layer, with over the opening on the alignment region comprising a recessed region and on the device region comprising a plurality of holes therein to expose the underlying dielectric layer. The exposed dielectric layer on the device region is etched to form contact holes therein.

摘要翻译： 使用部分凹入的硬掩模形成接触孔的方法。 提供具有装置区域和其中具有开口的对准区域的基板，用作对准标记。 形成覆盖在基板上并填充开口的电介质层。 在电介质层上形成多晶硅层，其中对准区域上的开口包括凹陷区域，并且在其上包括多个孔的器件区域上露出下面的介电层。 蚀刻器件区域上的暴露的电介质层以在其中形成接触孔。

公开(公告)号：US20070018341A1

公开(公告)日：2007-01-25

申请号：US11540392

申请日：2006-09-29

申请人： Wen-Kuei Hsieh ,  Hui-Min Mao ,  Yi-Nan Chen

发明人： Wen-Kuei Hsieh ,  Hui-Min Mao ,  Yi-Nan Chen

IPC分类号： H01L23/544

CPC分类号： H01L23/544 ,  H01L21/31144 ,  H01L21/76802 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming contact holes using a partially recessed hard mask. A substrate with a device region and an alignment region having an opening therein, acting as an alignment mark, is provided. A dielectric layer is formed overlying the substrate and fills the opening. A polysilicon layer is formed on the dielectric layer, with over the opening on the alignment region comprising a recessed region and on the device region comprising a plurality of holes therein to expose the underlying dielectric layer. The exposed dielectric layer on the device region is etched to form contact holes therein.

摘要翻译： 使用部分凹入的硬掩模形成接触孔的方法。 提供具有装置区域和其中具有开口的对准区域的基板，用作对准标记。 形成覆盖在基板上并填充开口的电介质层。 在电介质层上形成多晶硅层，其中对准区域上的开口包括凹陷区域，并且在其上包括多个孔的器件区域上露出下面的介电层。 蚀刻器件区域上的暴露的电介质层以在其中形成接触孔。

公开(公告)号：US06969686B2

公开(公告)日：2005-11-29

申请号：US10353177

申请日：2003-01-28

申请人： Wen-Kuei Hsieh ,  Chih-Mu Huang ,  James Juen Hsu

发明人： Wen-Kuei Hsieh ,  Chih-Mu Huang ,  James Juen Hsu

IPC分类号： H01L21/308 ,  H01L21/762 ,  H01L21/8239 ,  H01L27/105 ,  H01L21/302

CPC分类号： H01L27/105 ,  H01L21/3081 ,  H01L21/76229 ,  H01L27/1052

摘要： A method for manufacturing a memory device utilizes multi-etching processes to respectively construct isolation trenches in a memory substrate that has a memory array area and a peripheral circuit region, wherein the depth of the trenches in the peripheral circuit region is deeper into the memory substrate than the depth of the trenches in the memory array area. Therefore, possible current leakage caused from the high operating voltage is effectively mitigated, and the performance of the memory device is increased.

摘要翻译： 一种用于制造存储器件的方法利用多次蚀刻工艺来分别在具有存储器阵列区域和外围电路区域的存储器衬底中构建隔离沟槽，其中外围电路区域中的沟槽的深度更深于存储器衬底 比存储器阵列区域中的沟槽的深度高。 因此，可以有效地缓解由高工作电压引起的可能的电流泄漏，并且提高存储器件的性能。

公开(公告)号：US06762095B1

公开(公告)日：2004-07-13

申请号：US10250007

申请日：2003-05-28

申请人： Wen-Kuei Hsieh

发明人： Wen-Kuei Hsieh

IPC分类号： H01L21336

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11546

摘要： A method of fabricating flash memory is provided. A substrate divided into a memory cell region and a peripheral circuit region is provided. After forming a first conductive layer over the substrate, the first conductive layer in the memory cell region is patterned to form a first gate conductive layer. Thereafter, a gate dielectric layer is formed over the substrate and then a second conductive layer and a passivation layer are sequentially formed over the gate dielectric layer. After removing the passivation layer, the second conductive layer and the first conductive layer in the peripheral circuit region, a third conductive layer is formed over the substrate. The third conductive layer and the passivation layer in the memory cell region are removed. The second conductive layer, the gate dielectric layer and the first gate conductive layer in the memory cell region are patterned to form a plurality of memory gates. Finally, the third conductive layer in the peripheral circuit region is patterned to form a plurality of gates.

摘要翻译： 提供了一种制造闪速存储器的方法。 提供分为存储单元区域和外围电路区域的基板。 在衬底上形成第一导电层之后，将存储单元区域中的第一导电层图案化以形成第一栅极导电层。 此后，在衬底上形成栅极电介质层，然后在栅极介电层上依次形成第二导电层和钝化层。 在除去钝化层之后，外围电路区域中的第二导电层和第一导电层，在基板上形成第三导电层。 去除存储单元区域中的第三导电层和钝化层。 将存储单元区域中的第二导电层，栅极介电层和第一栅极导电层图案化以形成多个存储器栅极。 最后，外围电路区域中的第三导电层被图案化以形成多个栅极。

公开(公告)号：US06605509B1

公开(公告)日：2003-08-12

申请号：US10251962

申请日：2002-09-23

申请人： Wen-Kuei Hsieh

发明人： Wen-Kuei Hsieh

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method for forming a smooth floating gate structure for a flash memory is disclosed. The method comprises the following steps. A substrate is firstly provided, and a first conductive layer and a second conductive layer are sequentially formed on the substrate. A first dielectric layer is then formed on the second conductive layer. A first hard mask layer and a second hard mask layer are formed sequentially on the first dielectric layer. A floating gate pattern is then transferred into the second hard mask layer to expose the first hard mask layer. The first hard mask layer is then etched to form a pattern and expose the first dielectric layer. A second dielectric layer is conformally formed over the second hard mask layer and the pattern; The second dielectric layer is etched back to form a spacer and expose the first dielectric layer. The first dielectric layer is then etched to expose the second conductive layer and the spacer, the second hard mask layer, the first hard mask layer and the first dielectric layer are finally removed.

摘要翻译： 公开了一种用于形成用于闪速存储器的平滑浮动栅极结构的方法。 该方法包括以下步骤。 首先提供衬底，并且在衬底上依次形成第一导电层和第二导电层。 然后在第二导电层上形成第一介电层。 第一硬掩模层和第二硬掩模层依次形成在第一介电层上。 然后将浮栅图案转移到第二硬掩模层中以暴露第一硬掩模层。 然后蚀刻第一硬掩模层以形成图案并暴露第一介电层。 在第二硬掩模层和图案上共形形成第二电介质层; 将第二电介质层回蚀以形成间隔物并露出第一介电层。 然后蚀刻第一介电层以露出第二导电层，并且最终去除第二介电层，间隔物，第二硬掩模层，第一硬掩模层和第一介电层。

公开(公告)号：US07517811B2

公开(公告)日：2009-04-14

申请号：US10409226

申请日：2003-04-08

申请人： Wen-Kuei Hsieh

发明人： Wen-Kuei Hsieh

IPC分类号： H01L21/302

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method for fabricating a floating gate of the flash memories is described. A pad oxide layer and a silicon nitride layer are formed sequentially on a substrate. A plurality of shallow trenches is formed in the substrate and an active area is defined by the shallow trenches. The silicon nitride layer is pulled back by isotropic etching to expose the corner of the trench. A corner-rounding process is performed to round the corner. An STI structure is formed in the shallow trench. Thereafter, the pad oxide layer and the silicon nitride layer are removed. A tunneling oxide layer and a first polysilicon layer are formed sequentially on the active area and the first polysilicon layer is as high as the STI structure. A second polysilicon layer is formed on the first polysilicon layer and the STI structures. A portion of the second polysilicon layer on the STI structure is removed to form the floating gate.

摘要翻译： 描述了一种用于制造闪存的浮动栅极的方法。 在基板上依次形成焊盘氧化物层和氮化硅层。 在衬底中形成多个浅沟槽，并且有源区域由浅沟槽限定。 通过各向同性蚀刻将氮化硅层拉回以暴露沟槽的拐角。 执行一个四舍五入的过程，围绕角落。 在浅沟槽中形成STI结构。 此后，除去焊盘氧化物层和氮化硅层。 在有源区上依次形成隧穿氧化物层和第一多晶硅层，第一多晶硅层与STI结构一样高。 在第一多晶硅层和STI结构上形成第二多晶硅层。 STI结构上的第二多晶硅层的一部分被去除以形成浮栅。

公开(公告)号：US06472265B1

公开(公告)日：2002-10-29

申请号：US09562683

申请日：2000-05-02

申请人： Wen-Kuei Hsieh

发明人： Wen-Kuei Hsieh

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  H01L21/28518 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10873 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7834

摘要： A method of manufacturing an embedded DRAM. A substrate has a memory cell region and a logic circuit region. A plurality of gate conductors are formed on the substrate in the memory cell region and the logic circuit region. A spacer is formed on a sidewall of each gate conductor. An epitaxy layer is formed selectively on the exposed area of the substrate surface to service as source/drain regions in the logic circuit region and a source region and a drain region in the memory cell region. A silicide layer is formed on the epitaxy layer. A conformal buffer layer is formed over the substrate, and then a dielectric layer is formed over the substrate to cover the gate conductors. A mask is formed on the dielectric layer to expose a DRAM cell bit line contact region and a logic device source/drain contact region at the same time. A first etching step is performed to remove the dielectric layer by using the barrier layer as an etching stop layer. Then, a second etching step is performed to remove the barrier layer for exposing the silicide layer. As a result, a DRAM cell bit line contact and a logic device source/drain contact in the memory cell region and in the logic circuit region are formed at the same time by using the first etching step and the second etching step. Finally, metal plugs are formed within the DRAM cell bit line contact and the logic device source/drain contact simultaneously.

摘要翻译： 一种制造嵌入式DRAM的方法。 衬底具有存储单元区域和逻辑电路区域。 在存储单元区域和逻辑电路区域中的基板上形成多个栅极导体。 在每个栅极导体的侧壁上形成间隔物。 选择性地在衬底表面的暴露区域上形成外延层以用作逻辑电路区域中的源极/漏极区域以及存储器单元区域中的源极区域和漏极区域。 在外延层上形成硅化物层。 在衬底上形成共形缓冲层，然后在衬底上形成介电层以覆盖栅极导体。 在电介质层上形成掩模以同时暴露DRAM单元位线接触区域和逻辑器件源极/漏极接触区域。 通过使用阻挡层作为蚀刻停止层，进行第一蚀刻步骤以去除电介质层。 然后，执行第二蚀刻步骤以去除用于暴露硅化物层的阻挡层。 结果，通过使用第一蚀刻步骤和第二蚀刻步骤，同时形成存储单元区域和逻辑电路区域中的DRAM单元位线接触和逻辑器件源极/漏极接触。 最后，在DRAM单元位线触点和逻辑器件源极/漏极触点同时形成金属插头。

公开(公告)号：US06352896B1

公开(公告)日：2002-03-05

申请号：US09618597

申请日：2000-07-17

申请人： Haochieh Liu ,  Hsi-Chuan Chen ,  Jung-Ho Chang ,  Hong-Hsiang Tsai ,  Li-Ming Wang ,  Sen-Huan Huang ,  Bor-Ru Sheu ,  Wen-Kuei Hsieh

发明人： Haochieh Liu ,  Hsi-Chuan Chen ,  Jung-Ho Chang ,  Hong-Hsiang Tsai ,  Li-Ming Wang ,  Sen-Huan Huang ,  Bor-Ru Sheu ,  Wen-Kuei Hsieh

IPC分类号： H01L218242

CPC分类号： H01L27/10855 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10888

摘要： A method of manufacturing DRAM capacitor. An active region is formed above a substrate. A plurality of parallel word lines is formed above the substrate. A first plug and a second plug are formed between the word lines in locations for forming the desired bit line contact and node contact, respectively. Insulation material is deposited into the remaining space between the word lines. A bit line contact is formed above the first plug. A plurality of parallel bit lines is formed above the substrate. The bit lines are perpendicular to the word lines. The bit line is electrically connected to the substrate through the bit line contact and the first plug. The bit lines are electrically insulated from each other. Furthermore, each bit line is covered on top by a hard material layer. Finally, a node contact is formed over the second plug.

摘要翻译： 制造DRAM电容器的方法。 在衬底上形成有源区。 在基板上方形成多条平行字线。 第一插头和第二插头分别形成在用于形成所需位线接触和节点接触的位置之间的字线之间。 绝缘材料沉积在字线之间的剩余空间中。 在第一插头上形成位线接触。 在衬底上形成多个并行位线。 位线垂直于字线。 位线通过位线接触和第一插头与衬底电连接。 位线彼此电绝缘。 此外，每个位线由硬材料层覆盖在顶部。 最后，在第二插头上形成节点接触。