公开(公告)号：US06969686B2

公开(公告)日：2005-11-29

申请号：US10353177

申请日：2003-01-28

申请人： Wen-Kuei Hsieh ,  Chih-Mu Huang ,  James Juen Hsu

发明人： Wen-Kuei Hsieh ,  Chih-Mu Huang ,  James Juen Hsu

IPC分类号： H01L21/308 ,  H01L21/762 ,  H01L21/8239 ,  H01L27/105 ,  H01L21/302

CPC分类号： H01L27/105 ,  H01L21/3081 ,  H01L21/76229 ,  H01L27/1052

摘要： A method for manufacturing a memory device utilizes multi-etching processes to respectively construct isolation trenches in a memory substrate that has a memory array area and a peripheral circuit region, wherein the depth of the trenches in the peripheral circuit region is deeper into the memory substrate than the depth of the trenches in the memory array area. Therefore, possible current leakage caused from the high operating voltage is effectively mitigated, and the performance of the memory device is increased.

摘要翻译： 一种用于制造存储器件的方法利用多次蚀刻工艺来分别在具有存储器阵列区域和外围电路区域的存储器衬底中构建隔离沟槽，其中外围电路区域中的沟槽的深度更深于存储器衬底 比存储器阵列区域中的沟槽的深度高。 因此，可以有效地缓解由高工作电压引起的可能的电流泄漏，并且提高存储器件的性能。

公开(公告)号：US20050260811A1

公开(公告)日：2005-11-24

申请号：US10851044

申请日：2004-05-20

申请人： Chih-Fu Chang ,  Yen-Hsiu Chen ,  Hung-Jen Lin ,  Ming-Chu King ,  Ching-Hwano Su ,  Chih-Mu Huang ,  Yun Chang

发明人： Chih-Fu Chang ,  Yen-Hsiu Chen ,  Hung-Jen Lin ,  Ming-Chu King ,  Ching-Hwano Su ,  Chih-Mu Huang ,  Yun Chang

IPC分类号： C23C30/00 ,  H01L21/02 ,  H01L21/20 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/8242

CPC分类号： H01L21/2855 ,  H01L21/32051 ,  H01L28/60

摘要： A novel, low-temperature metal deposition method which is suitable for depositing a metal film on a substrate, such as in the fabrication of metal-insulator-metal (MIM) capacitors, is disclosed. The method includes depositing a metal film on a substrate using a deposition temperature of less than typically about 270 degrees C. The resulting metal film is characterized by enhanced thickness uniformity and reduced grain agglomeration which otherwise tends to reduce the operational integrity of a capacitor or other device of which the metal film is a part. Furthermore, the metal film is characterized by intrinsic breakdown voltage (Vbd) improvement.

摘要翻译： 公开了一种适用于在金属 - 绝缘体 - 金属（MIM）电容器的制造中在基底上沉积金属膜的新颖的低温金属沉积方法。 该方法包括使用小于一般约270℃的沉积温度在基板上沉积金属膜。所得到的金属膜的特征在于增强的厚度均匀性和减小的晶粒聚集，否则倾向于降低电容器或其它的操作完整性 金属膜是其一部分的装置。 此外，金属膜的特征在于本征击穿电压（V BAT）改善。

公开(公告)号：US06541325B2

公开(公告)日：2003-04-01

申请号：US10136118

申请日：2002-05-01

申请人： Chih-Mu Huang ,  Chuan-Jane Chao ,  Chi-Hung Kao

发明人： Chih-Mu Huang ,  Chuan-Jane Chao ,  Chi-Hung Kao

IPC分类号： H01L218238

CPC分类号： H01L28/40 ,  H01L27/0635

摘要： The present invention discloses a simple and convenient method for fabricating a capacitor device with BiCMOS processes. An electrode of the capacitor device formed according to the present invention is an ion doping region formed in an epitaxy layer so that the thickness of the dielectric layer of the capacitor device decreased relative to a specific ion concentration. Accordingly, the capacitor device formed therein has a high capacitance and good performance.

公开(公告)号：US07368775B2

公开(公告)日：2008-05-06

申请号：US10903084

申请日：2004-07-31

申请人： Chih-Mu Huang ,  Mingchu King ,  Yun Chang

发明人： Chih-Mu Huang ,  Mingchu King ,  Yun Chang

IPC分类号： H01L29/72

CPC分类号： H01L27/1085 ,  H01L27/10805 ,  H01L27/10873

摘要： A single transistor planar DRAM memory cell with improved charge retention and reduced current leakage and a method for forming the same, the method including providing a semiconductor substrate; forming a gate dielectric on the semiconductor substrate; forming a pass transistor structure adjacent a storage capacitor structure on the gate dielectric; forming sidewall spacer dielectric portions adjacent either side of the pass transistor to include covering a space between the pass transistor and the storage capacitor; forming a photoresist mask portion covering the pass transistor and exposing the storage capacitor; and, carrying out a P type ion implantation and drive in process to form a P doped channel region in the semiconductor substrate underlying the storage capacitor.

摘要翻译： 具有改善的电荷保持和减少的电流泄漏的单晶体管平面DRAM存储单元及其形成方法，所述方法包括提供半导体衬底; 在所述半导体衬底上形成栅电介质; 在所述栅极电介质上形成与所述存储电容器结构相邻的传输晶体管结构; 形成与所述传输晶体管的任一侧相邻的侧壁间隔物介质部分，以包括覆盖所述传输晶体管和所述存储电容器之间的空间; 形成覆盖所述通过晶体管并暴露所述存储电容器的光致抗蚀剂掩模部分; 并且进行P型离子注入和驱动，以在存储电容器下面的半导体衬底中形成P掺杂沟道区。

公开(公告)号：US07087483B2

公开(公告)日：2006-08-08

申请号：US10723072

申请日：2003-11-25

申请人： Chih-Mu Huang ,  Mingchu King ,  Yun Chang

发明人： Chih-Mu Huang ,  Mingchu King ,  Yun Chang

IPC分类号： H01L21/8242

CPC分类号： H01L27/10805 ,  H01L27/10888

摘要： A single transistor planar RAM memory cell with improved charge retention and a method for forming the same, the method including providing forming a pass transistor structure adjacent a storage capacitor structure separated by a predetermined distance; carrying out a first ion implantation process to form first and second doped regions adjacent either side of the pass transistor structure, the first doped region defined by the predetermined distance; depositing a spacer dielectric layer; etching back the spacer dielectric layer to leave an unetched spacer dielectric layer portion overlying the first doped region while forming a sidewall spacer of a predetermined width overlying a first portion of the second doped region; and, carrying out a second ion implantation process to form a relatively higher dopant concentration in a second portion of the second doped region.

摘要翻译： 具有改善的电荷保持的单晶体管平面RAM存储单元及其形成方法，所述方法包括提供与隔开预定距离的存储电容器结构相邻的传输晶体管结构; 执行第一离子注入工艺以形成邻近传输晶体管结构的任一侧的第一和第二掺杂区域，所述第一掺杂区域由所述预定距离限定; 沉积间隔电介质层; 蚀刻间隔电介质层以留下覆盖第一掺杂区的未蚀刻间隔物介电层部分，同时形成覆盖第二掺杂区域的第一部分的预定宽度的侧壁间隔物; 以及进行第二离子注入工艺以在所述第二掺杂区域的第二部分中形成相对较高的掺杂剂浓度。

公开(公告)号：US07176081B2

公开(公告)日：2007-02-13

申请号：US10851044

申请日：2004-05-20

申请人： Chih-Fu Chang ,  Yen-Hsiu Chen ,  Hung-Jen Lin ,  Ming-Chu King ,  Ching-Hwanq Su ,  Chih-Mu Huang ,  Yun Chang

发明人： Chih-Fu Chang ,  Yen-Hsiu Chen ,  Hung-Jen Lin ,  Ming-Chu King ,  Ching-Hwanq Su ,  Chih-Mu Huang ,  Yun Chang

IPC分类号： H01L21/8242

CPC分类号： H01L21/2855 ,  H01L21/32051 ,  H01L28/60

摘要： A novel, low-temperature metal deposition method which is suitable for depositing a metal film on a substrate, such as in the fabrication of metal-insulator-metal (MIM) capacitors, is disclosed. The method includes depositing a metal film on a substrate using a deposition temperature of less than typically about 270 degrees C. The resulting metal film is characterized by enhanced thickness uniformity and reduced grain agglomeration which otherwise tends to reduce the operational integrity of a capacitor or other device of which the metal film is a part. Furthermore, the metal film is characterized by intrinsic breakdown voltage (Vbd) improvement.

摘要翻译： 公开了一种适用于在金属 - 绝缘体 - 金属（MIM）电容器的制造中在基底上沉积金属膜的新颖的低温金属沉积方法。 该方法包括使用小于一般约270℃的沉积温度在基板上沉积金属膜。所得到的金属膜的特征在于增强的厚度均匀性和减小的晶粒聚集，否则倾向于降低电容器或其它的操作完整性 金属膜是其一部分的装置。 此外，金属膜的特征在于本征击穿电压（V BAT）改善。

公开(公告)号：US20060022240A1

公开(公告)日：2006-02-02

申请号：US10903084

申请日：2004-07-31

申请人： Chih-Mu Huang ,  Mingchu King ,  Yun Chang

发明人： Chih-Mu Huang ,  Mingchu King ,  Yun Chang

IPC分类号： H01L21/8244 ,  H01L29/94

CPC分类号： H01L27/1085 ,  H01L27/10805 ,  H01L27/10873

摘要： A single transistor planar DRAM memory cell with improved charge retention and reduced current leakage and a method for forming the same, the method including providing a semiconductor substrate; forming a gate dielectric on the semiconductor substrate; forming a pass transistor structure adjacent a storage capacitor structure on the gate dielectric; forming sidewall spacer dielectric portions adjacent either side of the pass transistor to include covering a space between the pass transistor and the storage capacitor; forming a photoresist mask portion covering the pass transistor and exposing the storage capacitor; and, carrying out a P type ion implantation and drive in process to form a P doped channel region in the semiconductor substrate underlying the storage capacitor.

摘要翻译： 具有改善的电荷保持和减少的电流泄漏的单晶体管平面DRAM存储单元及其形成方法，所述方法包括提供半导体衬底; 在所述半导体衬底上形成栅电介质; 在所述栅极电介质上形成与所述存储电容器结构相邻的传输晶体管结构; 形成邻近所述传输晶体管的任一侧的侧壁间隔物介质部分，以包括覆盖所述传输晶体管和所述存储电容器之间的空间; 形成覆盖所述通过晶体管并暴露所述存储电容器的光致抗蚀剂掩模部分; 并且进行P型离子注入和驱动，以在存储电容器下面的半导体衬底中形成P掺杂沟道区。

公开(公告)号：US20050110063A1

公开(公告)日：2005-05-26

申请号：US10723072

申请日：2003-11-25

申请人： Chih-Mu Huang ,  Mingchu King ,  Yun Chang

发明人： Chih-Mu Huang ,  Mingchu King ,  Yun Chang

IPC分类号： H01L21/8239 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76

CPC分类号： H01L27/10805 ,  H01L27/10888

摘要： A single transistor planar RAM memory cell with improved charge retention and a method for forming the same, the method including providing forming a pass transistor structure adjacent a storage capacitor structure separated by a predetermined distance; carrying out a first ion implantation process to form first and second doped regions adjacent either side of the pass transistor structure, the first doped region defined by the predetermined distance; depositing a spacer dielectric layer; etching back the spacer dielectric layer to leave an unetched spacer dielectric layer portion overlying the first doped region while forming a sidewall spacer of a predetermined width overlying a first portion of the second doped region; and, carrying out a second ion implantation process to form a relatively higher dopant concentration in a second portion of the second doped region.

摘要翻译： 具有改善的电荷保持的单晶体管平面RAM存储单元及其形成方法，所述方法包括提供与隔开预定距离的存储电容器结构相邻的传输晶体管结构; 执行第一离子注入工艺以形成邻近传输晶体管结构的任一侧的第一和第二掺杂区域，所述第一掺杂区域由所述预定距离限定; 沉积间隔电介质层; 蚀刻间隔电介质层以留下覆盖第一掺杂区的未蚀刻间隔物介电层部分，同时形成覆盖第二掺杂区域的第一部分的预定宽度的侧壁间隔物; 以及进行第二离子注入工艺以在所述第二掺杂区域的第二部分中形成相对较高的掺杂剂浓度。

公开(公告)号：US06292393B1

公开(公告)日：2001-09-18

申请号：US09531197

申请日：2000-03-20

申请人： Jung-Yu Tsai ,  Chih-Mu Huang ,  Chi-Hung Kao ,  Chuan-Jane Chao

发明人： Jung-Yu Tsai ,  Chih-Mu Huang ,  Chi-Hung Kao ,  Chuan-Jane Chao

IPC分类号： G11C700

CPC分类号： G11C16/20

摘要： A method is used to fully extract coupling coefficients of a flash memory cell by a GIDL manner. The flash memory cell is composed of a substrate, a drain region, source region, a control gate and a floating gate. The method keeps the source voltage Vs and the substrate voltage Vb fixed. The drain voltage Vd and the control gate voltage are varied. Then, measuring a GIDL current obtains a first coefficient ratio of the drain coupling coefficient ad to the gate coupling &agr;cg, that is, &agr;d/&agr;cg. Similarly, keeping the drain voltage Vd and the substrate voltage Vb fixed and varying the source voltage Vs and the control gate voltage Vcg, a second coefficient ratio of the source coupling coefficient &agr;s to the gate coupling coefficient &agr;cg, that is, &agr;s/&agr;cg. Similarly, keeping the drain voltage Vd and the source voltage Vs fixed and varying the control gate voltage Vcg and the substrate voltage Vb, a third coefficient ratio of the substrate coupling coefficient &agr;b to the gate coupling coefficient &agr;cg, that is, &agr;b/&agr;cg. The first coefficient ratio &agr;d/&agr;cg, the second coefficient ratio &agr;s/&agr;cg, and the third coefficient ratio &agr;b/&agr;cg incorporate a normalization equation of &agr;d+&agr;s+&agr;b+&agr;cg=1, so that all four coefficients &agr;d, &agr;s, &agr;b, and &agr;cg can be exactly solved.

摘要翻译： 一种方法用于通过GIDL方式完全提取闪存单元的耦合系数。 闪存单元由衬底，漏极区域，源极区域，控制栅极和浮动栅极组成。 该方法保持源极电压Vs和衬底电压Vb固定。 漏极电压Vd和控制栅极电压变化。 然后，测量GIDL电流获得排水耦合系数ad与门耦合alphacg的第一系数比，即alphad / alphacg。 类似地，保持漏极电压Vd和衬底电压Vb固定并改变源极电压Vs和控制栅极电压Vcg，源耦合系数αα的第二系数比与门耦合系数alphacg，即alphas / alphacg。 类似地，保持漏极电压Vd和源极电压Vs固定，并且改变控制栅极电压Vcg和衬底电压Vb，衬底耦合系数alphab与栅极耦合系数alphacg的第三系数比，即alphab / alphacg。 第一系数比alphad / alphacg，第二系数比alphas / alphacg和第三系数比alphab / alphacg包含alphad + alphas + alphab + alphacg = 1的归一化方程，使得所有四个系数alphad，alphas，alphab， 和alphacg可以精确解决。

公开(公告)号：US20060240624A1

公开(公告)日：2006-10-26

申请号：US11472941

申请日：2006-06-22

申请人： Chih-Mu Huang ,  Mingchu King ,  Yun Chang

发明人： Chih-Mu Huang ,  Mingchu King ,  Yun Chang

IPC分类号： H01L21/336

CPC分类号： H01L27/10805 ,  H01L27/10888

摘要： A single transistor planar RAM memory cell with improved charge retention and a method for forming the same, the method including providing forming a pass transistor structure adjacent a storage capacitor structure separated by a predetermined distance; carrying out a first ion implantation process to form first and second doped regions adjacent either side of the pass transistor structure, the first doped region defined by the predetermined distance; depositing a spacer dielectric layer; etching back the spacer dielectric layer to leave an unetched spacer dielectric layer portion overlying the first doped region while forming a sidewall spacer of a predetermined width overlying a first portion of the second doped region; and, carrying out a second ion implantation process to form a relatively higher dopant concentration in a second portion of the second doped region.