Wireless multiprocessor system-on-chip with unified memory and fault inhibitor
    7.
    发明申请
    Wireless multiprocessor system-on-chip with unified memory and fault inhibitor 有权
    具有统一存储器和故障抑制器的无线多处理器片上系统

    公开(公告)号:US20050148358A1

    公开(公告)日:2005-07-07

    申请号:US10841739

    申请日:2004-05-06

    申请人: Jian Lin Nicholas Yu

    发明人: Jian Lin Nicholas Yu

    IPC分类号: H04B7/185 H04M1/725

    摘要: Wireless mobile communication device includes unified memory portion; processing units coupled with, and communicating through, unified memory; fault inhibitor coupled with unified memory inhibiting operational fault from nocent informon. Memory, fault inhibitor, and processing units fabricated on monolithic integrated circuit as system-on-chip disposed in wireless mobile personal host. Multiprocessor module includes fault inhibitor and applications and communications processing units and buses, coupled with unified memory. Integrated functional constituent can include coprocessor, accelerator, operational control unit, interprocessor controller, memory controller, bus management unit, bridge, arbiters, and transceiver. Method inhibits operational fault from nocent informon, setting device in operational or fallback state.

    摘要翻译: 无线移动通信设备包括统一存储器部分; 处理单元加上并通过统一记忆进行通信; 故障抑制器加上统一的记忆功能,禁止无效信息的操作故障。 存储器,故障抑制器和单片集成电路上制造的处理单元,作为芯片上系统布置在无线移动个人主机中。 多处理器模块包括故障抑制器和应用以及通信处理单元和总线,以及统一存储器。 集成功能组件可以包括协处理器,加速器,操作控制单元,处理器间控制器,存储器控制器,总线管理单元,桥接器,仲裁器和收发器。 方法禁止无效信号的操作故障,将设备设置为运行或后备状态。