公开(公告)号：US20070018230A1

公开(公告)日：2007-01-25

申请号：US11490768

申请日：2006-07-21

申请人： Weon-Ho Park ,  Byoung-Ho Kim ,  Sang-Woo Kang ,  Jeong-Uk Han ,  Sung-Woo Park

发明人： Weon-Ho Park ,  Byoung-Ho Kim ,  Sang-Woo Kang ,  Jeong-Uk Han ,  Sung-Woo Park

IPC分类号： H01L29/788

CPC分类号： H01L29/7881 ,  H01L29/40114 ,  H01L29/42336 ,  H01L29/66825

摘要： An EEPROM includes a tunneling opening having an inclined or a stepped sidewall. A tunnel insulation layer is formed within the tunneling opening. Using a flowed photoresist pattern as an etching mask, the gate insulator is etched to form a tunneling opening having an inclined sidewall. Thus, the tunnel insulation layer can be formed in a smaller area than an area defined by a photolithography. As a result, a width of an active region and a width of a wordline are decreased to reduce a unit cell size.

摘要翻译： EEPROM包括具有倾斜或阶梯状侧壁的隧道开口。 在隧道开口内形成隧道绝缘层。 使用流动的光致抗蚀剂图案作为蚀刻掩模，蚀刻栅极绝缘体以形成具有倾斜侧壁的隧道开口。 因此，隧道绝缘层可以形成在比由光刻限定的区域更小的区域中。 结果，有效区域的宽度和字线的宽度减小以减小单元电池尺寸。

公开(公告)号：US20070298571A1

公开(公告)日：2007-12-27

申请号：US11896560

申请日：2007-09-04

申请人： Weon-Ho Park ,  Sang-Soo Kim ,  Hyun-Khe Yoo ,  Sung-Chul Park ,  Byoung-Ho Kim ,  Ju-Ri Kim ,  Seung-Beom Yoon ,  Jeong-Uk Han

发明人： Weon-Ho Park ,  Sang-Soo Kim ,  Hyun-Khe Yoo ,  Sung-Chul Park ,  Byoung-Ho Kim ,  Ju-Ri Kim ,  Seung-Beom Yoon ,  Jeong-Uk Han

IPC分类号： H01L21/8247

CPC分类号： H01L27/11526 ,  H01L21/76224 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823892 ,  H01L27/0922 ,  H01L27/105 ,  H01L27/11546

摘要： A device is described comprising a substrate of a first conductivity type having a first dopant concentration, a first well formed in the substrate, a second well of the first conductivity type formed in the substrate and being deeper than the first well, the second well having a higher dopant concentration than the first dopant concentration, and a nonvolatile memory cell formed on the second well. A device is described comprising four wells of various conductivity types with a nonvolatile memory cell formed on the second well. A device is described comprising a plurality of wells for isolating transistors of a plurality of voltage ranges, wherein each one of the plurality of wells contains at least one transistor of a particular voltage range, and wherein transistors of only one of the plurality of voltage ranges are within each of the plurality of wells. A method is described of isolating transistors of a first voltage range from transistors of another voltage range, comprising forming a first well to hold transistors only of a first particular voltage range, and forming a second well to hold transistors only of a second particular voltage range.

摘要翻译： 描述了一种器件，其包括具有第一掺杂剂浓度的第一导电类型的衬底，在衬底中形成的第一阱，在衬底中形成并且比第一阱更深的第一导电类型的第二阱，第二阱具有 比第一掺杂剂浓度高的掺杂剂浓度，以及形成在第二阱上的非易失性存储单元。 描述了一种装置，其包括具有形成在第二阱上的非易失性存储单元的各种导电类型的四个阱。 描述了一种器件，其包括用于隔离多个电压范围的晶体管的多个阱，其中多个阱中的每一个阱包含特定电压范围的至少一个晶体管，并且其中仅一个电压范围的晶体管 在多个孔的每一个内。 描述了一种将第一电压范围的晶体管与另一电压范围的晶体管隔离的方法，包括形成第一阱以仅保持第一特定电压范围的晶体管，以及形成第二阱以仅将晶体管保持在第二特定电压范围 。

公开(公告)号：US07323740B2

公开(公告)日：2008-01-29

申请号：US10870166

申请日：2004-06-18

申请人： Weon-Ho Park ,  Sang-Soo Kim ,  Hyun-Khe Yoo ,  Sung-Chul Park ,  Byoung-Ho Kim ,  Ju-Ri Kim ,  Seung-Beom Yoon ,  Jeong-Uk Han

发明人： Weon-Ho Park ,  Sang-Soo Kim ,  Hyun-Khe Yoo ,  Sung-Chul Park ,  Byoung-Ho Kim ,  Ju-Ri Kim ,  Seung-Beom Yoon ,  Jeong-Uk Han

IPC分类号： H01L29/788

CPC分类号： H01L27/11526 ,  H01L21/76224 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823892 ,  H01L27/0922 ,  H01L27/105 ,  H01L27/11546

摘要： A device is described comprising a substrate of a first conductivity type having a first dopant concentration, a first well formed in the substrate, a second well of the first conductivity type formed in the substrate and being deeper than the first well, the second well having a higher dopant concentration than the first dopant concentration, and a nonvolatile memory cell formed on the second well. A device is described comprising four wells of various conductivity types with a nonvolatile memory cell formed on the second well. A device is described comprising a plurality of wells for isolating transistors of a plurality of voltage ranges, wherein each one of the plurality of wells contains at least one transistor of a particular voltage range, and wherein transistors of only one of the plurality of voltage ranges are within each of the plurality of wells. A method is described of isolating transistors of a first voltage range from transistors of another voltage range, comprising forming a first well to hold transistors only of a first particular voltage range, and forming a second well to hold transistors only of a second particular voltage range.

摘要翻译： 描述了一种器件，其包括具有第一掺杂剂浓度的第一导电类型的衬底，在衬底中形成的第一阱，在衬底中形成并且比第一阱更深的第一导电类型的第二阱，第二阱具有 比第一掺杂剂浓度高的掺杂剂浓度，以及形成在第二阱上的非易失性存储单元。 描述了一种装置，其包括具有形成在第二阱上的非易失性存储单元的各种导电类型的四个阱。 描述了一种器件，其包括用于隔离多个电压范围的晶体管的多个阱，其中多个阱中的每一个阱包含特定电压范围的至少一个晶体管，并且其中仅一个电压范围的晶体管 在多个孔的每一个内。 描述了一种将第一电压范围的晶体管与另一电压范围的晶体管隔离的方法，包括形成第一阱以仅保持第一特定电压范围的晶体管，以及形成第二阱以仅将晶体管保持在第二特定电压范围 。

公开(公告)号：US07598139B2

公开(公告)日：2009-10-06

申请号：US11896560

申请日：2007-09-04

申请人： Weon-Ho Park ,  Sang-Soo Kim ,  Hyun-Khe Yoo ,  Sung-Chul Park ,  Byoung-Ho Kim ,  Ju-Ri Kim ,  Seung-Beom Yoon ,  Jeong-Uk Han

发明人： Weon-Ho Park ,  Sang-Soo Kim ,  Hyun-Khe Yoo ,  Sung-Chul Park ,  Byoung-Ho Kim ,  Ju-Ri Kim ,  Seung-Beom Yoon ,  Jeong-Uk Han

IPC分类号： H01L21/336

CPC分类号： H01L27/11526 ,  H01L21/76224 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823892 ,  H01L27/0922 ,  H01L27/105 ,  H01L27/11546

摘要： A device is described comprising a substrate of a first conductivity type having a first dopant concentration, a first well formed in the substrate, a second well of the first conductivity type formed in the substrate and being deeper than the first well, the second well having a higher dopant concentration than the first dopant concentration, and a nonvolatile memory cell formed on the second well. A device is described comprising four wells of various conductivity types with a nonvolatile memory cell formed on the second well. A device is described comprising a plurality of wells for isolating transistors of a plurality of voltage ranges, wherein each one of the plurality of wells contains at least one transistor of a particular voltage range, and wherein transistors of only one of the plurality of voltage ranges are within each of the plurality of wells. A method is described of isolating transistors of a first voltage range from transistors of another voltage range, comprising forming a first well to hold transistors only of a first particular voltage range, and forming a second well to hold transistors only of a second particular voltage range.

摘要翻译： 描述了一种器件，其包括具有第一掺杂剂浓度的第一导电类型的衬底，在衬底中形成的第一阱，在衬底中形成并且比第一阱更深的第一导电类型的第二阱，第二阱具有 比第一掺杂剂浓度高的掺杂剂浓度，以及形成在第二阱上的非易失性存储单元。 描述了一种装置，其包括具有形成在第二阱上的非易失性存储单元的各种导电类型的四个阱。 描述了一种器件，其包括用于隔离多个电压范围的晶体管的多个阱，其中多个阱中的每一个阱包含特定电压范围的至少一个晶体管，并且其中仅一个电压范围的晶体管 在多个孔的每一个内。 描述了一种将第一电压范围的晶体管与另一电压范围的晶体管隔离的方法，包括形成第一阱以仅保持第一特定电压范围的晶体管，以及形成第二阱以仅将晶体管保持在第二特定电压范围 。

公开(公告)号：US20060044915A1

公开(公告)日：2006-03-02

申请号：US11216677

申请日：2005-08-31

申请人： Ji-Hoon Park ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Seong-Gyun Kim ,  Sung-Taeg Kang ,  Bo-Young Seo ,  Sang-Woo Kang ,  Sung-Woo Park

发明人： Ji-Hoon Park ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Seong-Gyun Kim ,  Sung-Taeg Kang ,  Bo-Young Seo ,  Sang-Woo Kang ,  Sung-Woo Park

IPC分类号： G11C7/00

CPC分类号： H01L29/7881 ,  H01L27/11526 ,  H01L27/11534 ,  H01L29/42324 ,  H01L29/66795 ,  H01L29/785

摘要： A flash memory device according to the present invention includes a semiconductor fin including a top surface and a side surface originated from different crystal planes. The flash memory device comprises: insulating layers having different thicknesses formed on a side surface and a top surface of the semiconductor fin, a storage electrode, a gate insulating layer and a control gate electrode sequentially formed on the insulating layers. A thin insulating layer enables charges to be injected or emitted through it, and a thick insulating layer increases a coupling ratio. Accordingly, it is possible to increase an efficiency of a programming or an erase operation of a flash memory device.

摘要翻译： 根据本发明的闪速存储器件包括半导体鳍片，其包括由不同晶面产生的顶表面和侧表面。 闪存器件包括：在半导体鳍片的侧表面和顶表面上形成不同厚度的绝缘层，在绝缘层上依次形成的存储电极，栅极绝缘层和控制栅电极。 薄的绝缘层能够通过电荷注入或发射电荷，并且厚的绝缘层增加耦合比。 因此，可以提高闪速存储器件的编程或擦除操作的效率。

公开(公告)号：US07285820B2

公开(公告)日：2007-10-23

申请号：US11216677

申请日：2005-08-31

申请人： Ji-Hoon Park ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Seong-Gyun Kim ,  Sung-Taeg Kang ,  Bo-Young Seo ,  Sang-Woo Kang ,  Sung-Woo Park

发明人： Ji-Hoon Park ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Seong-Gyun Kim ,  Sung-Taeg Kang ,  Bo-Young Seo ,  Sang-Woo Kang ,  Sung-Woo Park

IPC分类号： H01L29/788

CPC分类号： H01L29/7881 ,  H01L27/11526 ,  H01L27/11534 ,  H01L29/42324 ,  H01L29/66795 ,  H01L29/785

摘要： A flash memory device according to the present invention includes a semiconductor fin including a top surface and a side surface originated from different crystal planes. The flash memory device comprises: insulating layers having different thicknesses formed on a side surface and a top surface of the semiconductor fin, a storage electrode, a gate insulating layer and a control gate electrode sequentially formed on the insulating layers. A thin insulating layer enables charges to be injected or emitted through it, and a thick insulating layer increases a coupling ratio. Accordingly, it is possible to increase an efficiency of a programming or an erase operation of a flash memory device.

摘要翻译： 根据本发明的闪速存储器件包括半导体鳍片，其包括由不同晶面产生的顶表面和侧表面。 闪存器件包括：在半导体鳍片的侧表面和顶表面上形成不同厚度的绝缘层，在绝缘层上依次形成的存储电极，栅极绝缘层和控制栅电极。 薄的绝缘层能够通过电荷注入或发射电荷，并且厚的绝缘层增加耦合比。 因此，可以提高闪速存储器件的编程或擦除操作的效率。

公开(公告)号：US20080054345A1

公开(公告)日：2008-03-06

申请号：US11891605

申请日：2007-08-10

申请人： Weon-Ho Park ,  Jeong-Uk Han ,  Yong-Tae Kim

发明人： Weon-Ho Park ,  Jeong-Uk Han ,  Yong-Tae Kim

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/42324 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/1203

摘要： An electrically erasable and programmable read only memory (EEPROM) device and a method of manufacturing the EEPROM device are provided. First and second gate structures having the same structure are formed on a tunnel insulating layer formed on a substrate, such that the first and second gate structures are spaced apart from each other. A common source region is formed at a portion of the substrate located between the first and second gate structures. First and second drain regions are formed at first and second portions of the substrate adjacent to the first and second gate structures, respectively. Thus, the EEPROM device is manufactured including first and second transistors that have the same structure and may alternately serve as a memory transistor and a selection transistor according to an applied signal.

摘要翻译： 提供电可擦除可编程只读存储器（EEPROM）器件和制造EEPROM器件的方法。 在形成在基板上的隧道绝缘层上形成具有相同结构的第一和第二栅极结构，使得第一和第二栅极结构彼此间隔开。 在位于第一和第二栅极结构之间的衬底的一部分处形成公共源区。 第一和第二漏极区分别形成在与第一和第二栅极结构相邻的衬底的第一和第二部分处。 因此，制造EEPROM器件，其包括具有相同结构的第一和第二晶体管，并且可以根据施加的信号交替地用作存储晶体管和选择晶体管。

公开(公告)号：US20080268592A1

公开(公告)日：2008-10-30

申请号：US12004698

申请日：2007-12-21

申请人： Weon-Ho Park ,  Jeong-Uk Han ,  Yong-Tae Kim

发明人： Weon-Ho Park ,  Jeong-Uk Han ,  Yong-Tae Kim

IPC分类号： H01L21/8242

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7881

摘要： Provided are a flash memory device and a method of fabricating the same. The method includes forming a first dielectric layer on an active region of a semiconductor substrate. A first conductive layer is formed on the semiconductor substrate having the first dielectric layer. A mask pattern is formed on the first conductive layer. Using the mask pattern as an etch mask, the first conductive layer is etched to form a first conductive pattern narrowing from its upper surface toward its middle portion. A second dielectric layer is formed on the semiconductor substrate having the first conductive pattern. A second conductive pattern crossing the active region adjacent to the first conductive pattern and partially covering the first conductive pattern is formed on the semiconductor substrate having the second dielectric layer.

摘要翻译： 提供一种闪速存储器件及其制造方法。 该方法包括在半导体衬底的有源区上形成第一电介质层。 在具有第一介电层的半导体衬底上形成第一导电层。 在第一导电层上形成掩模图案。 使用掩模图案作为蚀刻掩模，蚀刻第一导电层以形成从其上表面向其中间部分变窄的第一导电图案。 在具有第一导电图案的半导体衬底上形成第二电介质层。 在具有第二介电层的半导体衬底上形成与第一导电图案相邻的有源区域交叉并部分覆盖第一导电图案的第二导电图案。

公开(公告)号：US20080111181A1

公开(公告)日：2008-05-15

申请号：US11982036

申请日：2007-11-01

申请人： Weon-Ho Park ,  Jeong-Uk Han ,  Yong-Tae Kim

发明人： Weon-Ho Park ,  Jeong-Uk Han ,  Yong-Tae Kim

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/7883 ,  G11C16/0441 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825

摘要： A nonvolatile memory (NVM) device includes a floating gate on a semiconductor substrate and a gate insulating layer between the semiconductor substrate and the floating gate. A tunnel insulating layer is disposed between the semiconductor substrate and the floating gate. The tunnel insulating layer is thinner than the gate insulating layer. A first inter-gate insulating layer is disposed on the floating gate, and a sensing gate is disposed on the first inter-gate insulating layer. The sensing gate covers a first portion of the floating gate. A control gate is disposed to cover a top surface and a sidewall of a second portion of the floating gate. A second inter-gate insulating layer is disposed between the control gate and the sensing gate and between the control gate and the floating gate. Operation methods and fabrication methods of the NVM device are also provided.

摘要翻译： 非易失性存储器（NVM）器件包括半导体衬底上的浮置栅极和半导体衬底与浮置栅极之间的栅极绝缘层。 隧道绝缘层设置在半导体衬底和浮动栅极之间。 隧道绝缘层比栅极绝缘层薄。 第一栅极间绝缘层设置在浮置栅极上，感测栅极设置在第一栅极间绝缘层上。 感测门覆盖浮动栅极的第一部分。 控制门设置成覆盖浮动栅极的第二部分的顶表面和侧壁。 第二栅极间绝缘层设置在控制栅极和感测栅极之间以及控制栅极和浮动栅极之间。 还提供了NVM设备的操作方法和制造方法。

公开(公告)号：US08097913B2

公开(公告)日：2012-01-17

申请号：US11891605

申请日：2007-08-10

申请人： Weon-Ho Park ,  Jeong-Uk Han ,  Yong-Tae Kim

发明人： Weon-Ho Park ,  Jeong-Uk Han ,  Yong-Tae Kim

IPC分类号： H01L27/115 ,  H01L21/8247

CPC分类号： H01L29/42324 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/1203

摘要： An electrically erasable and programmable read only memory (EEPROM) device and a method of manufacturing the EEPROM device are provided. First and second gate structures having the same structure are formed on a tunnel insulating layer formed on a substrate, such that the first and second gate structures are spaced apart from each other. A common source region is formed at a portion of the substrate located between the first and second gate structures. First and second drain regions are formed at first and second portions of the substrate adjacent to the first and second gate structures, respectively. Thus, the EEPROM device is manufactured including first and second transistors that have the same structure and may alternately serve as a memory transistor and a selection transistor according to an applied signal.

摘要翻译： 提供电可擦除可编程只读存储器（EEPROM）器件和制造EEPROM器件的方法。 在形成在基板上的隧道绝缘层上形成具有相同结构的第一和第二栅极结构，使得第一和第二栅极结构彼此间隔开。 在位于第一和第二栅极结构之间的衬底的一部分处形成公共源区。 第一和第二漏极区分别形成在与第一和第二栅极结构相邻的衬底的第一和第二部分处。 因此，制造EEPROM器件，其包括具有相同结构的第一和第二晶体管，并且可以根据施加的信号交替地用作存储晶体管和选择晶体管。