公开(公告)号：US6133799A

公开(公告)日：2000-10-17

申请号：US257228

申请日：1999-02-25

申请人： Wesley Favors, Jr. ,  Eric William MacDonald ,  Subir Mukherjee ,  Lynn Albert Warriner

发明人： Wesley Favors, Jr. ,  Eric William MacDonald ,  Subir Mukherjee ,  Lynn Albert Warriner

IPC分类号： H03K3/354 ,  H01L27/12 ,  H03K3/03 ,  H03B5/02

CPC分类号： H01L27/1203 ,  H03K3/0315 ,  H03K2217/0018

摘要： A voltage controlled ring oscillator (VCRO) that can operate at low voltage and provide a variable periodic output. A plurality of transistors form a ring oscillator and a selected transistor in the ring oscillator has a body which can float with respect to ground potential. The selected transistor has a threshold voltage which is controllable by a voltage applied to the transistor body. A control input is coupled to the transistor body such that the body of the transistor can be charged by the control input. Charging the body alters the threshold voltage of the transistor and thereby controls the oscillation frequency of the oscillator.

摘要翻译： 电压控制环形振荡器（VCRO），可在低电压下工作并提供可变的周期性输出。 多个晶体管形成环形振荡器，环形振荡器中选定的晶体管具有能够相对于地电位浮动的主体。 所选择的晶体管具有可由施加到晶体管体的电压控制的阈值电压。 控制输入​​耦合到晶体管本体，使得晶体管的主体可以由控制输入充电。 对体内充电改变晶体管的阈值电压，从而控制振荡器的振荡频率。

公开(公告)号：US06886106B2

公开(公告)日：2005-04-26

申请号：US09978358

申请日：2001-10-16

申请人： Bishop Chapman Brock ,  Gary Dale Carpenter ,  Amanda Christine Caswell ,  Eric William MacDonald ,  Timothy Joe Rubidoux

发明人： Bishop Chapman Brock ,  Gary Dale Carpenter ,  Amanda Christine Caswell ,  Eric William MacDonald ,  Timothy Joe Rubidoux

IPC分类号： G06F1/08 ,  G06F1/04 ,  G06F1/32 ,  H03K3/017

CPC分类号： G06F1/08

摘要： A method and apparatus for providing a dynamically alterable output clock from an input clock based on the value of an integer, where the integer can be modified continuously. The invention also provides a sample cycle output which is an enable pulse, having the width of the input clock cycle, that is asserted one or two input clock cycles prior to the rising edge alignment of the input and output clocks, that acts as a rising edge alignment enable signal, maintaining a one-to-one correspondence between the sample cycle assertions and rising edge alignment events, regardless of the dynamic changes in the value of the integer.

摘要翻译： 一种用于基于整数的值从输入时钟提供动态可变输出时钟的方法和装置，其中整数可以连续地修改。 本发明还提供了采样周期输出，其是具有输入时钟周期的宽度的使能脉冲，其在输入和输出时钟的上升沿对准之前被断言为一个或两个输入时钟周期，其作为上升沿 边缘对齐使能信号，在采样周期断言和上升沿对齐事件之间保持一一对应，而不管整数值的动态变化。