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公开(公告)号：US11630720B2
公开(公告)日：2023-04-18
申请号：US17357856
申请日：2021-06-24
Applicant: Western Digital Technologies, Inc.
Inventor： Parvaneh Alavi , Kai-Lung Cheng , Yun-Tzuo Lai , Haining Liu
IPC: G06F11/07
Abstract: A device that provides error recovery handling includes a processor that is configured to receive an error recovery request including error type information and a page address, where the error type information is mapped to a first error recovery technique. The processor may be configured to determine whether an error count associated with the flash memory circuit satisfies a first criterion and an error map associated with the flash memory circuit satisfies a second criterion, where the error count indicates a number of read errors that have occurred and the error map indicates blocks in which the read errors have occurred. The processor may be configured to utilize a second technique to attempt to recover data when the first and second criterions are satisfied, otherwise utilize the first technique to attempt to recover data, where the second technique is associated with recovering data stored in an offline flash memory circuit.
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公开(公告)号：US11630609B2
公开(公告)日：2023-04-18
申请号：US16937420
申请日：2020-07-23
Applicant: Western Digital Technologies, Inc.
Inventor： Haining Liu , YungLi Ji , Yun-Tzuo Lai , Ming-Yu Tai
IPC: G06F3/06
Abstract: Systems and methods are disclosed for scheduling access commands for a data storage device. A data storage device determines a layout of a plurality of non-volatile memory arrays. The data storage device also determine completed access statistics and pending access statistics for a first set of the plurality of non-volatile memory arrays during a monitoring period. The data storage device further generates a schedule based on the layout of the plurality of non-volatile memory arrays, the completed access statistics, and the pending access statistics and executes access commands based on schedule.
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公开(公告)号：US11068170B2
公开(公告)日：2021-07-20
申请号：US16751124
申请日：2020-01-23
Applicant: Western Digital Technologies, Inc.
Inventor： Haining Liu , Yuriy Pavlenko , George G. Artnak, Jr.
Abstract: A storage device may include a controller and a memory array including a plurality of dies arranged into a plurality of channels. In some examples, the controller may be configured to define, from the memory array, a plurality of die-sets based on respective chip enable lines associated with the plurality of dies, wherein each die-set of the plurality of die-sets includes at least one die from each of the plurality of channels; define, from a selected die-set of the plurality of die-sets, a plurality of blocksets, wherein each blockset includes a block from each die of the selected die-set; receive a unit of data to be stored; and issue commands that cause the unit of data to be stored in blocks of a selected blockset of the plurality of blocksets.
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公开(公告)号：US10373695B2
公开(公告)日：2019-08-06
申请号：US15396206
申请日：2016-12-30
Applicant: Western Digital Technologies, Inc.
Inventor： Richard David Barndt , Aldo Giovanni Cometti , Haining Liu , Jerry Lo
Abstract: Aspects of the disclosure provide methods and apparatus for handling Read Disturb and block errors in a non-volatile memory (NVM) device. An error level of both an aggressor page that causes Read Disturb errors and an error level of adjacent victim pages are obtained. The error level of the victim page is compared against a predetermined threshold error level to determine if the victim page is experiencing a high level of bit errors. If so, then the error level of the aggressor page is compared to the error level of the victim page to determine whether Read Disturb errors are actually occurring due to host reads of the aggressor page. By looking at both the aggressor and victim error levels, a more accurate determination of Read Disturb errors may be obtained, resulting in less unnecessary relocations of pages and blocks within an NVM for mitigating Read Disturb effects.
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公开(公告)号：US20180188984A1
公开(公告)日：2018-07-05
申请号：US15396547
申请日：2016-12-31
Applicant: Western Digital Technologies, Inc.
Inventor： Ming-Yu Tai , Yun-Tzuo Lai , Yung-Li Ji , Haining Liu
CPC classification number: G11C16/3495 , G06F3/0619 , G06F3/0655 , G06F3/0688 , G06F11/076 , G06F12/02 , G06F12/0246 , G06F12/0253 , G06F2212/1036 , G06F2212/1044 , G06F2212/7211 , G11C16/349
Abstract: A method, system, and apparatus are provided for retiring computer memory blocks. Two overall schemes are provided for separating poorly functioning blocks from normally functioning blocks. In a first scheme, after data relocation is finished, firmware remembers the old physical memory block. As soon as the system writes to the old physical memory block with new data, firmware issues a read again and receives back a count of error bits. If the returned error bits are still high, then the system identifies the block as being weak and retires the block. In a second scheme, firmware tracks statistics for data relocates, block reads, activity timers, among other statistics. If some blocks have abnormal activities (e.g., too many data relocates, too many reads, etc.), then the system may identify the block as being weak and may retire the physical memory block.
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Patent Agency Ranking
公开(公告)号：US11816338B2
公开(公告)日：2023-11-14
申请号：US17955432
申请日：2022-09-28
Applicant: Western Digital Technologies, Inc.
Inventor： Yun-Tzuo Lai , Haining Liu , Subhash Balakrishna Pillai
IPC: G06F3/06
CPC classification number: G06F3/0616 , G06F3/0647 , G06F3/0656 , G06F3/0659 , G06F3/0679
Abstract: A data storage device that provides priority-based internal data movement includes a controller communicatively coupled to volatile memory and to non-volatile memory circuits, where the controller is configured to queue requests in a plurality of queues in the volatile memory, where each of the requests is associated with one of a plurality of internal data movement command types. The controller is also configured to select one of the plurality of queues based on a prioritization of the plurality of internal data movement command types. The controller is also configured to determine that the selected queue includes at least one request of the associated internal data movement command type. The controller is also configured to issue the at least one request from the selected queue to at least one of the non-volatile memory circuits.
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公开(公告)号：US10552055B2
公开(公告)日：2020-02-04
申请号：US16370811
申请日：2019-03-29
Applicant: Western Digital Technologies, Inc.
Inventor： Haining Liu , Yuriy Pavlenko , George G. Artnak, Jr.
Abstract: A storage device may include a controller and a memory array including a plurality of dies arranged into a plurality of channels. In some examples, the controller may be configured to define, from the memory array, a plurality of die-sets based on respective chip enable lines associated with the plurality of dies, wherein each die-set of the plurality of die-sets includes at least one die from each of the plurality of channels; define, from a selected die-set of the plurality of die-sets, a plurality of blocksets, wherein each blockset includes a block from each die of the selected die-set; receive a unit of data to be stored; and issue commands that cause the unit of data to be stored in blocks of a selected blockset of the plurality of blocksets.
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公开(公告)号：US10380028B2
公开(公告)日：2019-08-13
申请号：US15396411
申请日：2016-12-30
Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
Inventor： Caesar Cheuk-Chow Cheung , Haining Liu , Subhash Balakrishna Pillai
IPC: G06F3/06 , G06F12/1009
Abstract: The subject technology provides for recovering a validity table for a data storage system. A set of logical addresses in a mapping table is partitioned into subsets of logical addresses. Each of the subsets of logical addresses is assigned to respective processor cores in the data storage system. Each of the processor cores is configured to check each logical address of the assigned subset of logical addresses in the mapping table for a valid physical address mapped to the logical address, for each valid physical address mapped to a logical address of the assigned subset of logical addresses, increment a validity count in a local validity table associated with a blockset of the non-volatile memory corresponding to the valid physical address, and update validity counts in a global validity table associated with respective blocksets of the non-volatile memory with the validity counts in the local validity table.
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公开(公告)号：US10255179B2
公开(公告)日：2019-04-09
申请号：US15396361
申请日：2016-12-30
Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
Inventor： YungLi Ji , Yun-Tzuo Lai , Haining Liu , Ming-Yu Tai
Abstract: A device that provides garbage collection read throttling includes at least one processor that is configured to receive a request to perform a garbage collection read command on one of a plurality of flash memory circuits. The at least one processor is configured to determine whether garbage collection read throttling is enabled, such as when a garbage collection read throttling criterion is satisfied. The at least one processor is configured to buffer the garbage collection read command when garbage collection read throttling is enabled and perform the garbage collection read command when garbage collection read throttling is disabled. When the garbage collection read throttling is enabled and the garbage collection read command is buffered, the at least one processor is configured to perform the buffered garbage collection read command when garbage collection read throttling is subsequently disabled.
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公开(公告)号：US11487437B2
公开(公告)日：2022-11-01
申请号：US17222861
申请日：2021-04-05
Applicant: Western Digital Technologies, Inc.
Inventor： Yun-Tzuo Lai , Haining Liu , Subhash Balakrishna Pillai
IPC: G06F3/06
Abstract: A data storage device that provides priority-based internal data movement includes a controller communicatively coupled to volatile memory and to non-volatile memory circuits, where the controller is configured to queue requests in a plurality of queues in the volatile memory, where each of the requests is associated with one of a plurality of internal data movement command types. The controller is also configured to select one of the plurality of queues based on a prioritization of the plurality of internal data movement command types. The controller is also configured to determine that the selected queue includes at least one request of the associated internal data movement command type. The controller is also configured to issue the at least one request from the selected queue to at least one of the non-volatile memory circuits.
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