公开(公告)号：US20090098732A1

公开(公告)日：2009-04-16

申请号：US11965368

申请日：2007-12-27

申请人： Whee Won CHO ,  Jung Geun Kim ,  Eun Soo Kim

发明人： Whee Won CHO ,  Jung Geun Kim ,  Eun Soo Kim

IPC分类号： H01L21/768

CPC分类号： H01L21/76804 ,  H01L21/76831

摘要： The present invention relates to a semiconductor device and a method of forming a contact plug of a semiconductor device. According to the method, a first dielectric layer is formed on a semiconductor substrate in which junction regions are formed. A hard mask is formed on the first dielectric layer. The hard mask and the first dielectric layer corresponding to the junction regions are etched to form trenches. Spacers are formed on sidewalls of the trenches. Contact holes are formed in the first dielectric layer using an etch process employing the spacers and the hard mask so that the junction regions are exposed. The contact holes are gap filled with a conductive material, thus forming contact plugs. Accordingly, bit lines can be easily formed on the contact plugs formed at narrow spaces with a high density.

摘要翻译： 本发明涉及半导体器件和形成半导体器件的接触插塞的方法。 根据该方法，在形成有接合区域的半导体基板上形成第一电介质层。 在第一电介质层上形成硬掩模。 对应于接合区域的硬掩模和第一介电层被蚀刻以形成沟槽。 间隙形成在沟槽的侧壁上。 使用使用间隔物和硬掩模的蚀刻工艺在第一介电层中形成接触孔，使得接合区域露出。 接触孔用导电材料间隙填充，从而形成接触塞。 因此，可以容易地在高密度的狭窄空间形成的接触塞上形成位线。

公开(公告)号：US08692376B2

公开(公告)日：2014-04-08

申请号：US13463071

申请日：2012-05-03

申请人： Jung Geun Kim ,  Whee Won Cho ,  Eun Soo Kim

发明人： Jung Geun Kim ,  Whee Won Cho ,  Eun Soo Kim

IPC分类号： H01L23/48

CPC分类号： H01L21/76883 ,  H01L21/3215 ,  H01L21/76825

摘要： A method of manufacturing a semiconductor device includes forming an interlayer dielectric layer, forming trenches by etching the interlayer dielectric layer, forming a copper (Cu) layer to fill the trenches, and implanting at least one of an inert element, a nonmetallic element, and a metallic element onto a surface of the Cu layer.

摘要翻译： 一种制造半导体器件的方法包括形成层间电介质层，通过蚀刻层间电介质层形成沟槽，形成铜（Cu）层以填充沟槽，以及注入惰性元素，非金属元素和 在Cu层的表面上的金属元素。

公开(公告)号：US20120280397A1

公开(公告)日：2012-11-08

申请号：US13463071

申请日：2012-05-03

申请人： Jung Geun KIM ,  Whee Won Cho ,  Eun Soo Kim

发明人： Jung Geun KIM ,  Whee Won Cho ,  Eun Soo Kim

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/76883 ,  H01L21/3215 ,  H01L21/76825

摘要： A method of manufacturing a semiconductor device includes forming an interlayer dielectric layer, forming trenches by etching the interlayer dielectric layer, forming a copper (Cu) layer to fill the trenches, and implanting at least one of an inert element, a nonmetallic element, and a metallic element onto a surface of the Cu layer.

摘要翻译： 一种制造半导体器件的方法包括形成层间电介质层，通过蚀刻层间电介质层形成沟槽，形成铜（Cu）层以填充沟槽，以及注入惰性元素，非金属元素和 在Cu层的表面上的金属元素。

公开(公告)号：US07851350B2

公开(公告)日：2010-12-14

申请号：US11965368

申请日：2007-12-27

申请人： Whee Won Cho ,  Jung Geun Kim ,  Eun Soo Kim

发明人： Whee Won Cho ,  Jung Geun Kim ,  Eun Soo Kim

IPC分类号： H01L21/4763

CPC分类号： H01L21/76804 ,  H01L21/76831

摘要： The present invention relates to a semiconductor device and a method of forming a contact plug of a semiconductor device. According to the method, a first dielectric layer is formed on a semiconductor substrate in which junction regions are formed. A hard mask is formed on the first dielectric layer. The hard mask and the first dielectric layer corresponding to the junction regions are etched to form trenches. Spacers are formed on sidewalls of the trenches. Contact holes are formed in the first dielectric layer using an etch process employing the spacers and the hard mask so that the junction regions are exposed. The contact holes are gap filled with a conductive material, thus forming contact plugs. Accordingly, bit lines can be easily formed on the contact plugs formed at narrow spaces with a high density.

摘要翻译： 本发明涉及半导体器件和形成半导体器件的接触插塞的方法。 根据该方法，在形成有接合区域的半导体基板上形成第一电介质层。 在第一电介质层上形成硬掩模。 对应于接合区域的硬掩模和第一介电层被蚀刻以形成沟槽。 间隙形成在沟槽的侧壁上。 使用使用间隔物和硬掩模的蚀刻工艺在第一介电层中形成接触孔，使得接合区域露出。 接触孔用导电材料间隙填充，从而形成接触塞。 因此，可以容易地在高密度的狭窄空间形成的接触塞上形成位线。

公开(公告)号：US07682900B2

公开(公告)日：2010-03-23

申请号：US11964298

申请日：2007-12-26

申请人： Eun Soo Kim ,  Whee Won Cho ,  Seung Hee Hong

发明人： Eun Soo Kim ,  Whee Won Cho ,  Seung Hee Hong

IPC分类号： H01L21/336

CPC分类号： H01L27/11524 ,  H01L27/11521

摘要： The invention relates to a method of fabricating a flash memory device. According to the method, select transistors and memory cells are formed on, and junctions are formed in a semiconductor substrate. The semiconductor substrate between a select transistor and an adjacent memory cell are over etched using a hard mask pattern. Accordingly, migration of electrons can be prohibited and program disturbance characteristics can be improved. Further, a void is formed between the memory cells. Accordingly, an interference phenomenon between the memory cells can be reduced and, therefore, the reliability of a flash memory device can be improved.

摘要翻译： 本发明涉及一种制造闪速存储器件的方法。 根据该方法，在半导体衬底中形成选择晶体管和存储单元，并且形成结。 选择晶体管和相邻存储单元之间的半导体衬底使用硬掩模图案过蚀刻。 因此，可以禁止电子的迁移，并且可以提高程序干扰特性。 此外，在存储单元之间形成空隙。 因此，可以减少存储单元之间的干扰现象，因此可以提高闪存器件的可靠性。

公开(公告)号：US07611964B2

公开(公告)日：2009-11-03

申请号：US12163584

申请日：2008-06-27

申请人： Jong Hye Cho ,  Whee Won Cho ,  Eun Soo Kim

发明人： Jong Hye Cho ,  Whee Won Cho ,  Eun Soo Kim

IPC分类号： H01L21/76

CPC分类号： H01L21/76232 ,  H01L27/11521

摘要： The present invention relates to a method of forming an isolation layer of a semiconductor memory device. According to a method of fabricating a semiconductor memory device in accordance with an aspect of the present invention, a tunnel insulating layer and a charge trap layer are formed over a semiconductor substrate. An isolation trench is formed by etching the charge trap layer and the tunnel insulating layer. A passivation layer is formed on the entire surface including the isolation trench. A first insulating layer is formed at a bottom of the isolation trench. Portions of the passivation layer, which are oxidized in the formation process of the first insulating layer, are removed. A second insulating layer is formed on the entire surface including the first insulating layer.

摘要翻译： 本发明涉及形成半导体存储器件的隔离层的方法。 根据本发明的半导体存储器件的制造方法，在半导体衬底上形成隧道绝缘层和电荷俘获层。 通过蚀刻电荷陷阱层和隧道绝缘层形成隔离沟槽。 在包括隔离沟槽的整个表面上形成钝化层。 第一绝缘层形成在隔离沟槽的底部。 去除在第一绝缘层的形成过程中被氧化的钝化层的部分。 在包括第一绝缘层的整个表面上形成第二绝缘层。

公开(公告)号：US20090004819A1

公开(公告)日：2009-01-01

申请号：US11963906

申请日：2007-12-24

申请人： Whee Won Cho ,  Eun Soo Kim ,  Suk Joong Kim

发明人： Whee Won Cho ,  Eun Soo Kim ,  Suk Joong Kim

IPC分类号： H01L21/76

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： In one aspect of the inventive method, a tunnel insulating film, a first conductive layer, and an isolation mask pattern are formed over a semiconductor substrate. The first conductive layer and the tunnel insulating film are patterned along the isolation mask pattern. A trench is formed in the semiconductor substrate. The trench is gap filled with a first insulating film. A polishing process is performed in order to expose the first conductive layer. A height of the first insulating film is lowered. The first conductive layer on the first insulating film is gap-filled with a second insulating film.

摘要翻译： 在本发明方法的一个方面中，在半导体衬底上形成隧道绝缘膜，第一导电层和隔离掩模图案。 第一导电层和隧道绝缘膜沿着隔离掩模图案被图案化。 在半导体衬底中形成沟槽。 沟槽填充有第一绝缘膜。 进行抛光处理以露出第一导电层。 第一绝缘膜的高度降低。 第一绝缘膜上的第一导电层用第二绝缘膜间隙填充。

公开(公告)号：US07504333B2

公开(公告)日：2009-03-17

申请号：US11614082

申请日：2006-12-21

申请人： Cheol Mo Jeong ,  Whee Won Cho ,  Eun Soo Kim ,  Seung Hee Hong

发明人： Cheol Mo Jeong ,  Whee Won Cho ,  Eun Soo Kim ,  Seung Hee Hong

IPC分类号： H01L21/20

CPC分类号： H01L21/76864 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/76846 ,  H01L21/76876

摘要： A method of forming a conductive structure (e.g., bit line) of a semiconductor device includes forming a barrier metal layer on a semiconductor substrate in which structures are formed. An amorphous titanium carbon nitride layer is formed on the barrier metal layer. A tungsten seed layer is formed on the amorphous titanium carbon nitride layer under an atmosphere including a boron gas. A tungsten layer is formed on the tungsten seed layer, thus forming a bit line.

摘要翻译： 形成半导体器件的导电结构（例如位线）的方法包括在形成结构的半导体衬底上形成阻挡金属层。 在阻挡金属层上形成非晶氮化钛层。 在包含硼气体的气氛下，在非晶态氮化钛层上形成钨种子层。 在钨籽晶层上形成钨层，形成位线。

公开(公告)号：US20080003742A1

公开(公告)日：2008-01-03

申请号：US11567218

申请日：2006-12-06

申请人： Whee Won Cho ,  Seung Hee Hong ,  Seong Hwan Myung ,  Eun Soo Kim

发明人： Whee Won Cho ,  Seung Hee Hong ,  Seong Hwan Myung ,  Eun Soo Kim

IPC分类号： H01L21/336

CPC分类号： H01L27/11521

摘要： A method of manufacturing flash memory devices increases a coupling ratio by increasing the height of a floating gate externally projecting from an isolation layer. A portion of the isolation layer between the floating gates is etched so that a control gate to be formed subsequently is located between the floating gates. Accordingly, an interference phenomenon can be reduced.

摘要翻译： 制造闪速存储器件的方法通过增加从隔离层外部突出的浮动栅极的高度来增加耦合比。 蚀刻浮置栅极之间的隔离层的一部分，使得随后形成的控制栅极位于浮置栅极之间。 因此，可以降低干扰现象。

公开(公告)号：US07560340B2

公开(公告)日：2009-07-14

申请号：US11567218

申请日：2006-12-06

申请人： Whee Won Cho ,  Seung Hee Hong ,  Seong Hwan Myung ,  Eun Soo Kim

发明人： Whee Won Cho ,  Seung Hee Hong ,  Seong Hwan Myung ,  Eun Soo Kim

IPC分类号： H01L21/336

CPC分类号： H01L27/11521

摘要： A method of manufacturing flash memory devices increases a coupling ratio by increasing the height of a floating gate externally projecting from an isolation layer. A portion of the isolation layer between the floating gates is etched so that a control gate to be formed subsequently is located between the floating gates. Accordingly, an interference phenomenon can be reduced.

摘要翻译： 制造闪速存储器件的方法通过增加从隔离层外部突出的浮动栅极的高度来增加耦合比。 蚀刻浮置栅极之间的隔离层的一部分，使得随后形成的控制栅极位于浮置栅极之间。 因此，可以降低干扰现象。