公开(公告)号：US07851350B2

公开(公告)日：2010-12-14

申请号：US11965368

申请日：2007-12-27

申请人： Whee Won Cho ,  Jung Geun Kim ,  Eun Soo Kim

发明人： Whee Won Cho ,  Jung Geun Kim ,  Eun Soo Kim

IPC分类号： H01L21/4763

CPC分类号： H01L21/76804 ,  H01L21/76831

摘要： The present invention relates to a semiconductor device and a method of forming a contact plug of a semiconductor device. According to the method, a first dielectric layer is formed on a semiconductor substrate in which junction regions are formed. A hard mask is formed on the first dielectric layer. The hard mask and the first dielectric layer corresponding to the junction regions are etched to form trenches. Spacers are formed on sidewalls of the trenches. Contact holes are formed in the first dielectric layer using an etch process employing the spacers and the hard mask so that the junction regions are exposed. The contact holes are gap filled with a conductive material, thus forming contact plugs. Accordingly, bit lines can be easily formed on the contact plugs formed at narrow spaces with a high density.

摘要翻译： 本发明涉及半导体器件和形成半导体器件的接触插塞的方法。 根据该方法，在形成有接合区域的半导体基板上形成第一电介质层。 在第一电介质层上形成硬掩模。 对应于接合区域的硬掩模和第一介电层被蚀刻以形成沟槽。 间隙形成在沟槽的侧壁上。 使用使用间隔物和硬掩模的蚀刻工艺在第一介电层中形成接触孔，使得接合区域露出。 接触孔用导电材料间隙填充，从而形成接触塞。 因此，可以容易地在高密度的狭窄空间形成的接触塞上形成位线。

公开(公告)号：US08692376B2

公开(公告)日：2014-04-08

申请号：US13463071

申请日：2012-05-03

申请人： Jung Geun Kim ,  Whee Won Cho ,  Eun Soo Kim

发明人： Jung Geun Kim ,  Whee Won Cho ,  Eun Soo Kim

IPC分类号： H01L23/48

CPC分类号： H01L21/76883 ,  H01L21/3215 ,  H01L21/76825

摘要： A method of manufacturing a semiconductor device includes forming an interlayer dielectric layer, forming trenches by etching the interlayer dielectric layer, forming a copper (Cu) layer to fill the trenches, and implanting at least one of an inert element, a nonmetallic element, and a metallic element onto a surface of the Cu layer.

摘要翻译： 一种制造半导体器件的方法包括形成层间电介质层，通过蚀刻层间电介质层形成沟槽，形成铜（Cu）层以填充沟槽，以及注入惰性元素，非金属元素和 在Cu层的表面上的金属元素。

公开(公告)号：US20090098732A1

公开(公告)日：2009-04-16

申请号：US11965368

申请日：2007-12-27

申请人： Whee Won CHO ,  Jung Geun Kim ,  Eun Soo Kim

发明人： Whee Won CHO ,  Jung Geun Kim ,  Eun Soo Kim

IPC分类号： H01L21/768

CPC分类号： H01L21/76804 ,  H01L21/76831

摘要： The present invention relates to a semiconductor device and a method of forming a contact plug of a semiconductor device. According to the method, a first dielectric layer is formed on a semiconductor substrate in which junction regions are formed. A hard mask is formed on the first dielectric layer. The hard mask and the first dielectric layer corresponding to the junction regions are etched to form trenches. Spacers are formed on sidewalls of the trenches. Contact holes are formed in the first dielectric layer using an etch process employing the spacers and the hard mask so that the junction regions are exposed. The contact holes are gap filled with a conductive material, thus forming contact plugs. Accordingly, bit lines can be easily formed on the contact plugs formed at narrow spaces with a high density.

摘要翻译： 本发明涉及半导体器件和形成半导体器件的接触插塞的方法。 根据该方法，在形成有接合区域的半导体基板上形成第一电介质层。 在第一电介质层上形成硬掩模。 对应于接合区域的硬掩模和第一介电层被蚀刻以形成沟槽。 间隙形成在沟槽的侧壁上。 使用使用间隔物和硬掩模的蚀刻工艺在第一介电层中形成接触孔，使得接合区域露出。 接触孔用导电材料间隙填充，从而形成接触塞。 因此，可以容易地在高密度的狭窄空间形成的接触塞上形成位线。

公开(公告)号：US08138077B2

公开(公告)日：2012-03-20

申请号：US12464947

申请日：2009-05-13

申请人： Whee Won Cho ,  Nam Woo So ,  Cheol Mo Jeong ,  Eun Gyeong Jang, legal representative ,  Jung Geun Kim

发明人： Whee Won Cho ,  Nam Woo So ,  Cheol Mo Jeong ,  Jung Geun Kim

IPC分类号： H01L29/788

CPC分类号： H01L21/28273 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7881

摘要： A flash memory device includes an isolation layer formed on an isolation region of a semiconductor substrate, a tunnel insulating layer formed on an active region of the semiconductor substrate, a first conductive layer formed over the tunnel insulating layer, a dielectric layer formed on the first conductive layer and the isolation layer, a first trench penetrating the dielectric layer on the isolation layer to separate parts of the dielectric layer, a second trench formed on the isolation layer and expanded from the first trench, and a second conductive layer formed over the dielectric layer to fill the first and second trenches.

摘要翻译： 闪速存储器件包括形成在半导体衬底的隔离区上的隔离层，形成在半导体衬底的有源区上的隧道绝缘层，形成在隧道绝缘层上的第一导电层，形成在第一 导电层和隔离层，穿过隔离层上的电介质层以分离电介质层的部分的第一沟槽，形成在隔离层上并从第一沟槽扩展的第二沟槽以及形成在电介质上的第二导电层 层以填充第一和第二沟槽。

公开(公告)号：US07521319B2

公开(公告)日：2009-04-21

申请号：US11646777

申请日：2006-12-28

申请人： Cheol Mo Jeong ,  Whee Won Cho ,  Jung Geun Kim ,  Seong Hwan Myung

发明人： Cheol Mo Jeong ,  Whee Won Cho ,  Jung Geun Kim ,  Seong Hwan Myung

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A method of forming a gate of a flash memory device, including the steps of forming a gate on a semiconductor substrate and forming an oxide layer on the entire surface of the gate, forming a nitride layer on a sidewall of the oxide layer in a spacer form, performing a polishing process so that a top surface of the gate is exposed, and then stripping the nitride layer to form an opening, forming a barrier metal layer on a sidewall of the opening, and forming a tungsten layer in the opening.

摘要翻译： 一种形成闪速存储器件的栅极的方法，包括以下步骤：在半导体衬底上形成栅极并在栅极的整个表面上形成氧化物层，在间隔物的氧化物层的侧壁上形成氮化物层 形成，进行抛光处理使得栅极的顶表面露出，然后剥离氮化物层以形成开口，在开口的侧壁上形成阻挡金属层，并在开口中形成钨层。

公开(公告)号：US07390714B2

公开(公告)日：2008-06-24

申请号：US11164804

申请日：2005-12-06

申请人： Cheol Mo Jeong ,  Whee Won Cho ,  Jung Geun Kim

发明人： Cheol Mo Jeong ,  Whee Won Cho ,  Jung Geun Kim

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  H01L27/11521

摘要： Disclosed herein is a method of manufacturing semiconductor devices. The method includes the steps of forming a gate oxide film, a polysilicon film and a nitride film on a semiconductor substrate, and patterning the gate oxide film, the polysilicon film and the nitride film to form poly gates, forming a spacer at the side of the poly gate, forming a sacrifice nitride film on the entire surface, and then forming an interlayer insulation film on the entire surface, polishing the sacrifice nitride film formed on the interlayer insulation film and the poly gates so that the nitride film is exposed, removing top portions of the sacrifice nitride film while removing the nitride film, forming an insulation film spacer at the side exposed through removal of the nitride film, and filling a portion from which the sacrifice oxide film is removed with an insulation film, and forming the tungsten gates in portions from which the nitride films are moved.

摘要翻译： 这里公开了半导体器件的制造方法。 该方法包括在半导体衬底上形成栅极氧化膜，多晶硅膜和氮化物膜的步骤，以及对栅极氧化膜，多晶硅膜和氮化物膜进行构图以形成多晶硅栅极，在 在整个表面上形成牺牲氮化物膜，然后在整个表面上形成层间绝缘膜，研磨在层间绝缘膜和多晶硅栅上形成的牺牲氮化物膜，使得氮化物膜露出，去除 牺牲氮化物膜的顶部，同时去除氮化物膜，在通过去除氮化物膜暴露的一侧形成绝缘膜间隔物，并且用绝缘膜填充去除牺牲氧化物膜的部分，并形成钨 栅极在其中移动氮化物膜的部分中。

公开(公告)号：US20080102579A1

公开(公告)日：2008-05-01

申请号：US11617690

申请日：2006-12-28

申请人： Cha Deok Dong ,  Whee Won Cho ,  Jung Geun Kim ,  Cheol Mo Jeong ,  Suk Joong Kim ,  Jung Gu Lee

发明人： Cha Deok Dong ,  Whee Won Cho ,  Jung Geun Kim ,  Cheol Mo Jeong ,  Suk Joong Kim ,  Jung Gu Lee

IPC分类号： H01L21/8242

CPC分类号： H01L27/11521 ,  H01L21/76232

摘要： A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. A spacer is formed on sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches. Each second trench is narrower and deeper than the corresponding first trench. A first oxide layer is formed on sidewalls and a bottom surface of each of the second trenches. The first trench is filled with an insulating layer.

摘要翻译： 形成半导体器件的隔离层的方法包括在半导体衬底的隔离区域中形成第一沟槽。 间隔件形成在每个第一沟槽的侧壁上。 第二沟槽形成在对应的第一沟槽下方的隔离区域中。 每个第二沟槽比相应的第一沟槽更窄和更深。 第一氧化物层形成在每个第二沟槽的侧壁和底表面上。 第一沟槽填充有绝缘层。

公开(公告)号：US07892919B2

公开(公告)日：2011-02-22

申请号：US12163328

申请日：2008-06-27

申请人： Jung Geun Kim ,  Cheol Mo Jeong ,  Whee Won Cho

发明人： Jung Geun Kim ,  Cheol Mo Jeong ,  Whee Won Cho

IPC分类号： H01L21/8242

CPC分类号： H01L21/76232

摘要： The invention discloses a method of forming an isolation layer in a semiconductor device. The method includes providing a semiconductor substrate having a trench formed therein; forming a first insulating layer in the trench; and forming a densified second insulating layer on the first insulating layer. In the above method, a void is not generated in the isolation layer so a bending phenomenon of an active region can be reduced or prevented to improve an electrical characteristic of the semiconductor.

摘要翻译： 本发明公开了一种在半导体器件中形成隔离层的方法。 该方法包括提供其中形成有沟槽的半导体衬底; 在沟槽中形成第一绝缘层; 以及在所述第一绝缘层上形成致密的第二绝缘层。 在上述方法中，在隔离层中不会产生空隙，因此可以减少或防止有源区的弯曲现象来改善半导体的电特性。

公开(公告)号：US20100304549A1

公开(公告)日：2010-12-02

申请号：US12815317

申请日：2010-06-14

申请人： Cha Deok DONG ,  Whee Won Cho ,  Jung Geun Kim ,  Cheol Mo Jeong ,  Suk Joong Kim ,  Jung Gu Lee

发明人： Cha Deok DONG ,  Whee Won Cho ,  Jung Geun Kim ,  Cheol Mo Jeong ,  Suk Joong Kim ,  Jung Gu Lee

IPC分类号： H01L21/76

CPC分类号： H01L27/11521 ,  H01L21/76232

摘要： A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. Sidewalls and a bottom surface of each of the first trenches are oxidized by a radical oxidization process to form a first oxide layer. An oxidization-prevention spacer is formed on the sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches, wherein each second trench is narrower and deeper than the corresponding first trench. The second trenches are filled with a second oxide layer. The first trenches are filled with an insulating layer.

摘要翻译： 形成半导体器件的隔离层的方法包括在半导体衬底的隔离区域中形成第一沟槽。 每个第一沟槽的侧壁和底表面被自由基氧化过程氧化以形成第一氧化物层。 在每个第一沟槽的侧壁上形成防氧化间隔物。 第二沟槽形成在对应的第一沟槽下方的隔离区域中，其中每个第二沟槽比相应的第一沟槽更窄和更深。 第二沟槽填充有第二氧化物层。 第一沟槽填充有绝缘层。

公开(公告)号：US20080003754A1

公开(公告)日：2008-01-03

申请号：US11646777

申请日：2006-12-28

申请人： Cheol Mo Jeong ,  Whee Won Cho ,  Jung Geun Kim ,  Seong Hwan Myung

发明人： Cheol Mo Jeong ,  Whee Won Cho ,  Jung Geun Kim ,  Seong Hwan Myung

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A method of forming a gate of a flash memory device, including the steps of forming a gate on a semiconductor substrate and forming an oxide layer on the entire surface of the gate, forming a nitride layer on a sidewall of the oxide layer in a spacer form, performing a polishing process so that a top surface of the gate is exposed, and then stripping the nitride layer to form an opening, forming a barrier metal layer on a sidewall of the opening, and forming a tungsten layer in the opening.

摘要翻译： 一种形成闪速存储器件的栅极的方法，包括以下步骤：在半导体衬底上形成栅极并在栅极的整个表面上形成氧化物层，在间隔物的氧化物层的侧壁上形成氮化物层 形成，进行抛光处理使得栅极的顶表面露出，然后剥离氮化物层以形成开口，在开口的侧壁上形成阻挡金属层，并在开口中形成钨层。