Method for forming a layered semiconductor technology structure and corresponding layered semiconductor technology structure
    1.
    发明授权
    Method for forming a layered semiconductor technology structure and corresponding layered semiconductor technology structure 失效
    形成层状半导体技术结构的方法和相应的分层半导体技术结构

    公开(公告)号:US07294564B2

    公开(公告)日:2007-11-13

    申请号:US10492329

    申请日:2002-10-11

    IPC分类号: H01L21/425

    摘要: The following invention provides a method for forming a layered semiconductor structure having a layer of a first semiconductor material on a substrate of at least one second semiconductor material, comprising the steps of: providing said substrate; burying said layer of said first semiconductor material in said substrate, said buried layer having an upper surface and a lower surface and dividing said substrate into an upper part and a lower part; creating a buried damage layer; which at least partly adjoins and/or partly includes said upper surface of said buried layer; and removing said upper part of said substrate and said buried damage layer for exposing said buried layer. The invention also provides a corresponding layered semiconductor structure.

    摘要翻译: 以下发明提供了一种在至少一个第二半导体材料的衬底上形成具有第一半导体材料层的层状半导体结构的方法,包括以下步骤:提供所述衬底; 将所述第一半导体材料的所述层埋入所述衬底中,所述掩埋层具有上表面和下表面,并将所述衬底分成上部和下部; 造成埋藏的破坏层; 其至少部分地邻接和/或部分地包括所述掩埋层的所述上表面; 以及去除所述衬底的所述上部和用于暴露所述掩埋层的所述掩埋损伤层。 本发明还提供了相应的分层半导体结构。

    Semiconductor layer structure comprising a cavity layer and method for fabricating the semiconductor layer structure
    2.
    发明授权
    Semiconductor layer structure comprising a cavity layer and method for fabricating the semiconductor layer structure 有权
    包括空腔层的半导体层结构和用于制造半导体层结构的方法

    公开(公告)号:US08829532B2

    公开(公告)日:2014-09-09

    申请号:US11702011

    申请日:2007-02-02

    摘要: Semiconductor layer structure and a method for producing a structure are provided, including a substrate made of semiconductor material, on which a layer made of a second semiconductor material is situated, furthermore a region (3) enriched with impurity atoms, which region is situated either in layer (2) or at a specific depth below the interface between layer (2) and substrate (1), additionally a layer (4) within the region (3) enriched with impurity atoms, which layer comprises cavities produced by ion implantation, furthermore at least one epitaxial layer (6) applied to layer (2) and also a defect region (5) comprising dislocations and stacking faults within the layer (4) comprising cavities, the at least one epitaxial layer (6) being largely crack-free, and a residual strain of the at least one epitaxial layer (6) being less than or equal to 1 GPa.

    摘要翻译: 提供半导体层结构和制造结构的方法,包括由半导体材料制成的基板,在其上设置由第二半导体材料制成的层,此外还包括富含杂质原子的区域(3),该区域位于 在层(2)中或在层(2)和衬底(1)之间的界面下方的特定深度处,另外在区域(3)内富含杂质原子的层(4),该层包括通过离子注入产生的空穴, 此外,施加到层(2)的至少一个外延层(6)还包括在包括空腔的层(4)内的位错和层叠缺陷的缺陷区域(5),所述至少一个外延层(6) 所述至少一个外延层(6)的残余应变小于或等于1GPa。

    SEMICONDUCTOR LAYER STRUCTURE AND METHOD FOR FABRICATING A SEMICONDUCTOR LAYER STRUCTURE
    3.
    发明申请
    SEMICONDUCTOR LAYER STRUCTURE AND METHOD FOR FABRICATING A SEMICONDUCTOR LAYER STRUCTURE 有权
    用于制造半导体层结构的半导体层结构和方法

    公开(公告)号:US20110151650A1

    公开(公告)日:2011-06-23

    申请号:US13038479

    申请日:2011-03-02

    IPC分类号: H01L21/20

    摘要: Semiconductor layer structure and a method for producing a structure are provided, including a substrate made of semiconductor material, on which a layer made of a second semiconductor material is situated, furthermore a region (3) enriched with impurity atoms, which region is situated either in layer (2) or at a specific depth below the interface between layer (2) and substrate (1), additionally a layer (4) within the region (3) enriched with impurity atoms, which layer comprises cavities produced by ion implantation, furthermore at least one epitaxial layer (6) applied to layer (2) and also a defect region (5) comprising dislocations and stacking faults within the layer (4) comprising cavities, the at least one epitaxial layer (6) being largely crack-free, and a residual strain of the at least one epitaxial layer (6) being less than or equal to 1 GPa.

    摘要翻译: 提供半导体层结构和制造结构的方法,包括由半导体材料制成的基板,在其上设置由第二半导体材料制成的层,此外还包括富含杂质原子的区域(3),该区域位于 在层(2)中或在层(2)和衬底(1)之间的界面下方的特定深度处,另外在区域(3)内富含杂质原子的层(4),该层包括通过离子注入产生的空穴, 此外,施加到层(2)的至少一个外延层(6)以及包括位于包括空腔的层(4)内的位错和堆垛层错的缺陷区域(5),所述至少一个外延层(6) 所述至少一个外延层(6)的残余应变小于或等于1GPa。