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    CMOS well structure and method of forming the same
    1.
    发明授权
    CMOS well structure and method of forming the same 失效
    CMOS阱结构及其形成方法

    公开(公告)号：US07709365B2

    公开(公告)日：2010-05-04

    申请号：US11551959

    申请日：2006-10-23

    申请人： Wilfried Haensch ,  Terence B. Hook ,  Louis C. Hsu ,  Rajiv V. Joshi ,  Werner Rausch

    发明人： Wilfried Haensch ,  Terence B. Hook ,  Louis C. Hsu ,  Rajiv V. Joshi ,  Werner Rausch

    IPC分类号： H01L21/22 ,  H01L21/38

    CPC分类号： H01L29/78 ,  H01L21/823892 ,  H01L27/0928

    摘要： A method for forming a CMOS well structure including forming a plurality of first conductivity type wells over a substrate, each of the plurality of first conductivity type wells formed in a respective opening in a first mask. A cap is formed over each of the first conductivity type wells, and the first mask is removed. Sidewall spacers are formed on sidewalls of each of the first conductivity type wells. A plurality of second conductivity type wells are formed, each of the plurality of second conductivity type wells are formed between respective first conductivity type wells. A plurality of shallow trench isolations are formed between the first conductivity type wells and second conductive type wells. The plurality of first conductivity type wells are formed by a first selective epitaxial growth process, and the plurality of second conductivity type wells are formed by a second selective epitaxial growth process.

    摘要翻译： 一种用于形成CMOS阱结构的方法，包括在衬底上形成多个第一导电类型阱，所述多个第一导电类型阱中的每一个形成在第一掩模中的相应开口中。 在每个第一导电类型的阱上形成盖，并且去除第一掩模。 在每个第一导电类型的孔的侧壁上形成侧壁间隔物。 形成多个第二导电型阱，多个第二导电型阱中的每一个形成在相应的第一导电型阱之间。 在第一导电型阱和第二导电类型阱之间形成多个浅沟槽隔离。 通过第一选择性外延生长工艺形成多个第一导电型阱，并且通过第二选择性外延生长工艺形成多个第二导电型阱。

    CMOS well structure and method of forming the same
    2.
    发明授权
    CMOS well structure and method of forming the same 有权
    CMOS阱结构及其形成方法

    公开(公告)号：US07132323B2

    公开(公告)日：2006-11-07

    申请号：US10713447

    申请日：2003-11-14

    申请人： Wilfried Haensch ,  Terence B. Hook ,  Louis C. Hsu ,  Rajiv V. Joshi ,  Werner Rausch

    发明人： Wilfried Haensch ,  Terence B. Hook ,  Louis C. Hsu ,  Rajiv V. Joshi ,  Werner Rausch

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/78 ,  H01L21/823892 ,  H01L27/0928

    摘要： A method for forming a CMOS well structure including forming a plurality of first conductivity type wells over a substrate, each of the plurality of first conductivity type wells formed in a respective opening in a first mask. A cap is formed over each of the first conductivity type wells, and the first mask is removed. Sidewall spacers are formed on sidewalls of each of the first conductivity type wells. A plurality of second conductivity type wells are formed, each of the plurality of second conductivity type wells are formed between respective first conductivity type wells. A plurality of shallow trench isolations are formed between the first conductivity type wells and second conductive type wells. The plurality of first conductivity type wells are formed by a first selective epitaxial growth process, and the plurality of second conductivity type wells are formed by a second selective epitaxial growth process.

    摘要翻译： 一种用于形成CMOS阱结构的方法，包括在衬底上形成多个第一导电类型阱，所述多个第一导电类型阱中的每一个形成在第一掩模中的相应开口中。 在每个第一导电类型的阱上形成盖，并且去除第一掩模。 在每个第一导电类型的孔的侧壁上形成侧壁间隔物。 形成多个第二导电型阱，多个第二导电型阱中的每一个形成在相应的第一导电型阱之间。 在第一导电型阱和第二导电类型阱之间形成多个浅沟槽隔离。 通过第一选择性外延生长工艺形成多个第一导电型阱，并且通过第二选择性外延生长工艺形成多个第二导电型阱。

    High performance FET with elevated source/drain region
    3.
    发明授权
    High performance FET with elevated source/drain region 失效
    具有升高的源极/漏极区域的高性能FET

    公开(公告)号：US07566599B2

    公开(公告)日：2009-07-28

    申请号：US10996866

    申请日：2004-11-24

    申请人： Rama Divakaruni ,  Louis C. Hsu ,  Rajiv V. Joshi ,  Carl J. Radens

    发明人： Rama Divakaruni ,  Louis C. Hsu ,  Rajiv V. Joshi ,  Carl J. Radens

    IPC分类号： H01L21/00

    CPC分类号： H01L29/66553 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/78618 ,  H01L29/78684

    摘要： A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETs. The FETs include a thin channel with raised source/drain (RSD) regions at each end on an insulator layer, e.g., on an ultra-thin silicon on insulator (SOI) chip. Isolation trenches at each end of the FETs, i.e., at the end of the RSD regions, isolate and define FET islands. Insulating sidewalls at each RSD region sandwich the FET gate between the RSD regions. The gate dielectric may be a high K dielectric. Salicide on the RSD regions and, optionally, on the gates reduce device resistances.

    摘要翻译： 包括FET的场效应晶体管（FET），集成电路（IC）芯片和形成FET的方法。 FET包括在绝缘体层上的每个端部（例如，在绝缘体上的超薄绝缘体（SOI））芯片上的源极/漏极（RSD）区域上升的薄沟道。 在FET的每个端部，即在RSD区域的末端处的隔离沟槽隔离并限定FET岛。 每个RSD区域的绝缘侧壁将RSD区域之间的FET栅极夹在中间。 栅极电介质可以是高K电介质。 RSD区域上和可选地在栅极上的杀菌剂降低了器件电阻。

    DIELECTRIC INTERCONNECT STRUCTURES AND METHODS FOR FORMING THE SAME
    5.
    发明申请
    DIELECTRIC INTERCONNECT STRUCTURES AND METHODS FOR FORMING THE SAME 有权
    介电互连结构及其形成方法

    公开(公告)号：US20090023286A1

    公开(公告)日：2009-01-22

    申请号：US12173899

    申请日：2008-07-16

    申请人： Chih-Chao Yang ,  Louis C. Hsu ,  Rajiv V. Joshi

    发明人： Chih-Chao Yang ,  Louis C. Hsu ,  Rajiv V. Joshi

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76834 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846

    摘要： Dielectric interconnect structures and methods for forming the same are provided. Specifically, the present invention provides a dielectric interconnect structure having a noble metal layer (e.g., Ru, Ir, Rh, Pt, RuTa, and alloys of Ru, Ir, Rh, Pt, and RuTa) that is formed directly on a modified dielectric surface. In a typical embodiment, the modified dielectric surface is created by treating an exposed dielectric layer of the interconnect structure with a gaseous ion plasma (e.g., Ar, He, Ne, Xe, N2, H2, NH3, and N2H2). Under the present invention, the noble metal layer could be formed directly on an optional glue layer that is maintained only on vertical surfaces of any trench or via formed in the exposed dielectric layer. In addition, the noble metal layer may or may not be provided along an interface between the via and an internal metal layer.

    摘要翻译： 提供介电互连结构及其形成方法。 具体地说，本发明提供一种具有贵金属层（例如，Ru，Ir，Rh，Pt，RuTa以及Ru，Ir，Rh，Pt和RuTa的合金）的电介质互连结构，其直接形成在改性电介质上 表面。 在典型的实施方案中，通过用气态离子等离子体（例如Ar，He，Ne，Xe，N 2，H 2，NH 3和N 2 H 2）处理互连结构的暴露介电层来产生修饰的电介质表面。 在本发明中，贵金属层可以直接形成在只保留在暴露的介电层中形成的任何沟槽或通孔的垂直表面上的任选的胶层上。 此外，贵金属层可以沿着通孔和内部金属层之间的界面设置也可以不设置。

    DIELECTRIC INTERCONNECT STRUCTURES AND METHODS FOR FORMING THE SAME
    6.
    发明申请
    DIELECTRIC INTERCONNECT STRUCTURES AND METHODS FOR FORMING THE SAME 有权
    介电互连结构及其形成方法

    公开(公告)号：US20080290518A1

    公开(公告)日：2008-11-27

    申请号：US12185759

    申请日：2008-08-04

    申请人： Chih-Chao Yang ,  Louis C. Hsu ,  Rajiv V. Joshi

    发明人： Chih-Chao Yang ,  Louis C. Hsu ,  Rajiv V. Joshi

    IPC分类号： H01L23/52

    CPC分类号： H01L21/76834 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846

    摘要： Dielectric interconnect structures and methods for forming the same are provided. Specifically, the present invention provides a dielectric interconnect structure having a noble metal layer (e.g., Ru, Ir, Rh, Pt, RuTa, and alloys of Ru, Ir, Rh, Pt, and RuTa) that is formed directly on a modified dielectric surface. In a typical embodiment, the modified dielectric surface is created by treating an exposed dielectric layer of the interconnect structure with a gaseous ion plasma (e.g., Ar, He, Ne, Xe, N2, H2, NH3, and N2H2). Under the present invention, the noble metal layer could be formed directly on an optional glue layer that is maintained only on vertical surfaces of any trench or via formed in the exposed dielectric layer. In addition, the noble metal layer may or may not be provided along an interface between the via and an internal metal layer.

    摘要翻译： 提供介电互连结构及其形成方法。 具体地说，本发明提供一种具有贵金属层（例如，Ru，Ir，Rh，Pt，RuTa以及Ru，Ir，Rh，Pt和RuTa的合金）的电介质互连结构，其直接形成在改性电介质上 表面。 在典型的实施方案中，通过用气态离子等离子体（例如Ar，He，Ne，Xe，N 2，H 2，NH 3和N 2 H 2）处理互连结构的暴露介电层来产生修饰的电介质表面。 在本发明中，贵金属层可以直接形成在只保留在暴露的介电层中形成的任何沟槽或通孔的垂直表面上的任选的胶层上。 此外，贵金属层可以沿着通孔和内部金属层之间的界面设置也可以不设置。

    Dielectric interconnect structures and methods for forming the same
    7.
    发明授权
    Dielectric interconnect structures and methods for forming the same 有权
    介电互连结构及其形成方法

    公开(公告)号：US07435674B2

    公开(公告)日：2008-10-14

    申请号：US11390390

    申请日：2006-03-27

    申请人： Chih-Chao Yang ,  Louis C. Hsu ,  Rajiv V. Joshi

    发明人： Chih-Chao Yang ,  Louis C. Hsu ,  Rajiv V. Joshi

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76834 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846

    摘要： Dielectric interconnect structures and methods for forming the same are provided. Specifically, the present invention provides a dielectric interconnect structure having a noble metal layer (e.g., Ru, Ir, Rh, Pt, RuTa, and alloys of Ru, Ir, Rh, Pt, and RuTa) that is formed directly on a modified dielectric surface. In a typical embodiment, the modified dielectric surface is created by treating an exposed dielectric layer of the interconnect structure with a gaseous ion plasma (e.g., Ar, He, Ne, Xe, N2, H2, NH3, and N2H2). Under the present invention, the noble metal layer could be formed directly on an optional glue layer that is maintained only on vertical surfaces of any trench or via formed in the exposed dielectric layer. In addition, the noble metal layer may or may not be provided along an interface between the via and an internal metal layer.

    摘要翻译： 提供介电互连结构及其形成方法。 具体地说，本发明提供一种具有贵金属层（例如，Ru，Ir，Rh，Pt，RuTa以及Ru，Ir，Rh，Pt和RuTa的合金）的电介质互连结构，其直接形成在改性电介质上 表面。 在典型的实施例中，通过用气态离子等离子体（例如，Ar，He，Ne，Xe，N 2，H，SUB）处理互连结构的暴露的电介质层来产生改性的电介质表面 > 2，NH 3和N 2 H 2）。 在本发明中，贵金属层可以直接形成在只保留在暴露的介电层中形成的任何沟槽或通孔的垂直表面上的任选的胶层上。 此外，贵金属层可以沿着通孔和内部金属层之间的界面设置也可以不设置。

    Fuse/anti-fuse structure and methods of making and programming same
    8.
    发明申请
    Fuse/anti-fuse structure and methods of making and programming same 失效
    保险丝/反熔丝结构及制作和编程方法相同

    公开(公告)号：US20080017858A1

    公开(公告)日：2008-01-24

    申请号：US11491721

    申请日：2006-07-24

    申请人： Louis C. Hsu ,  Rajiv V. Joshi ,  Jack Allan Mandelman ,  Chih-Chao Yang

    发明人： Louis C. Hsu ,  Rajiv V. Joshi ,  Jack Allan Mandelman ,  Chih-Chao Yang

    IPC分类号： H01L29/04

    CPC分类号： H01L23/5256 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Techniques are provided for fuse/anti-fuse structures, including an inner conductor structure, an insulating layer spaced outwardly of the inner conductor structure, an outer conductor structure disposed outwardly of the insulating layer, and a cavity-defining structure that defines a cavity, with at least a portion of the cavity-defining structure being formed from at least one of the inner conductor structure, the insulating layer, and the outer conductor structure. Methods of making and programming the fuse/anti-fuse structures are also provided.

    摘要翻译： 提供了用于熔丝/反熔丝结构的技术，包括内部导体结构，从内部导体结构向外间隔开的绝缘层，设置在绝缘层外部的外部导体结构，以及限定空腔的空腔限定结构， 其中所述空腔限定结构的至少一部分由所述内部导体结构，所述绝缘层和所述外部导体结构中的至少一个形成。 还提供了制造和编程保险丝/反熔丝结构的方法。

    Integrated circuit chip with FETs having mixed body thicknesses and method of manufacture thereof
    9.
    发明授权
    Integrated circuit chip with FETs having mixed body thicknesses and method of manufacture thereof 有权
    具有混合体厚度的FET的集成电路芯片及其制造方法

    公开(公告)号：US07285480B1

    公开(公告)日：2007-10-23

    申请号：US11279063

    申请日：2006-04-07

    申请人： Rajiv V. Joshi ,  Louis C. Hsu ,  Oleg Gluschenkov

    发明人： Rajiv V. Joshi ,  Louis C. Hsu ,  Oleg Gluschenkov

    IPC分类号： H01L21/00

    CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/78654

    摘要： An Integrated Circuit (IC) chip that may be a bulk CMOS IC chip with silicon on insulator (SOI) Field Effect Transistors (FETs) and method of making the chip. The IC chip includes areas with pockets of buried insulator strata and FETs formed on the strata are SOI FETs. The SOI FETs may include Partially Depleted SOI (PD-SOI) FETs and Fully Depleted SOI (FD-SOI) FETs and the chip may include bulk FETs as well. The FETs are formed by contouring the surface of a wafer, conformally implanting oxygen to a uniform depth, and planarizing to remove the Buried OXide (BOX) in bulk FET regions.

    摘要翻译： 一种集成电路（IC）芯片，其可以是具有绝缘体上硅（SOI）场效应晶体管（FET）和制造芯片的方法的体CMOS IC芯片。 IC芯片包括具有埋入绝缘体层的凹坑的区域，并且在层上形成的FET是SOI FET。 SOI FET可以包括部分耗尽的SOI（PD-SOI）FET和完全耗尽的SOI（FD-SOI）FET，并且芯片也可以包括体FET。 FET通过轮廓化晶片的表面，将氧气保形地均匀地注入到均匀的深度，并平坦化以去除体FET区域中的掩埋氧化物（BOX）来形成。

    High performance FET with elevated source/drain region
    10.
    发明授权
    High performance FET with elevated source/drain region 失效
    具有升高的源极/漏极区域的高性能FET

    公开(公告)号：US06864540B1

    公开(公告)日：2005-03-08

    申请号：US10851530

    申请日：2004-05-21

    申请人： Rama Divakaruni ,  Louis C. Hsu ,  Rajiv V. Joshi ,  Carl J. Radens

    发明人： Rama Divakaruni ,  Louis C. Hsu ,  Rajiv V. Joshi ,  Carl J. Radens

    IPC分类号： H01L21/336 ,  H01L29/45 ,  H01L29/76 ,  H01L29/786

    CPC分类号： H01L29/66553 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/78618 ,  H01L29/78684

    摘要： The invention includes a field effect transistor (FET) on an insulator layer, and integrated circuit (IC) on SOI chip including the FETs and a method of forming the IC. The FETs include a thin channel with raised source/drain (RSD) regions at each end on an insulator layer, e.g., on an ultra-thin silicon on insulator (SOI) chip. Isolation trenches at each end of the FETs, i.e., at the end of the RSD regions, isolate and define FET islands. Insulating sidewalls at each RSD region sandwich the FET gate between the RSD regions. The gate dielectric may be a high K dielectric. Salicide on the RSD regions and, optionally, on the gates reduce device resistances.

    摘要翻译： 本发明包括在绝缘体层上的场效应晶体管（FET）和包括FET的SOI芯片上的集成电路（IC）以及形成IC的方法。 FET包括在绝缘体层上的每个端部（例如，在绝缘体上的超薄绝缘体（SOI））芯片上的源极/漏极（RSD）区域上升的薄沟道。 在FET的每个端部，即在RSD区域的末端处的隔离沟槽隔离并限定FET岛。 每个RSD区域的绝缘侧壁将RSD区域之间的FET栅极夹在中间。 栅极电介质可以是高K电介质。 RSD区域上和可选地在栅极上的杀菌剂降低了器件电阻。