公开(公告)号：US07709365B2

公开(公告)日：2010-05-04

申请号：US11551959

申请日：2006-10-23

申请人： Wilfried Haensch ,  Terence B. Hook ,  Louis C. Hsu ,  Rajiv V. Joshi ,  Werner Rausch

发明人： Wilfried Haensch ,  Terence B. Hook ,  Louis C. Hsu ,  Rajiv V. Joshi ,  Werner Rausch

IPC分类号： H01L21/22 ,  H01L21/38

CPC分类号： H01L29/78 ,  H01L21/823892 ,  H01L27/0928

摘要： A method for forming a CMOS well structure including forming a plurality of first conductivity type wells over a substrate, each of the plurality of first conductivity type wells formed in a respective opening in a first mask. A cap is formed over each of the first conductivity type wells, and the first mask is removed. Sidewall spacers are formed on sidewalls of each of the first conductivity type wells. A plurality of second conductivity type wells are formed, each of the plurality of second conductivity type wells are formed between respective first conductivity type wells. A plurality of shallow trench isolations are formed between the first conductivity type wells and second conductive type wells. The plurality of first conductivity type wells are formed by a first selective epitaxial growth process, and the plurality of second conductivity type wells are formed by a second selective epitaxial growth process.

摘要翻译： 一种用于形成CMOS阱结构的方法，包括在衬底上形成多个第一导电类型阱，所述多个第一导电类型阱中的每一个形成在第一掩模中的相应开口中。 在每个第一导电类型的阱上形成盖，并且去除第一掩模。 在每个第一导电类型的孔的侧壁上形成侧壁间隔物。 形成多个第二导电型阱，多个第二导电型阱中的每一个形成在相应的第一导电型阱之间。 在第一导电型阱和第二导电类型阱之间形成多个浅沟槽隔离。 通过第一选择性外延生长工艺形成多个第一导电型阱，并且通过第二选择性外延生长工艺形成多个第二导电型阱。

公开(公告)号：US07132323B2

公开(公告)日：2006-11-07

申请号：US10713447

申请日：2003-11-14

申请人： Wilfried Haensch ,  Terence B. Hook ,  Louis C. Hsu ,  Rajiv V. Joshi ,  Werner Rausch

发明人： Wilfried Haensch ,  Terence B. Hook ,  Louis C. Hsu ,  Rajiv V. Joshi ,  Werner Rausch

IPC分类号： H01L21/8238

CPC分类号： H01L29/78 ,  H01L21/823892 ,  H01L27/0928

摘要： A method for forming a CMOS well structure including forming a plurality of first conductivity type wells over a substrate, each of the plurality of first conductivity type wells formed in a respective opening in a first mask. A cap is formed over each of the first conductivity type wells, and the first mask is removed. Sidewall spacers are formed on sidewalls of each of the first conductivity type wells. A plurality of second conductivity type wells are formed, each of the plurality of second conductivity type wells are formed between respective first conductivity type wells. A plurality of shallow trench isolations are formed between the first conductivity type wells and second conductive type wells. The plurality of first conductivity type wells are formed by a first selective epitaxial growth process, and the plurality of second conductivity type wells are formed by a second selective epitaxial growth process.

摘要翻译： 一种用于形成CMOS阱结构的方法，包括在衬底上形成多个第一导电类型阱，所述多个第一导电类型阱中的每一个形成在第一掩模中的相应开口中。 在每个第一导电类型的阱上形成盖，并且去除第一掩模。 在每个第一导电类型的孔的侧壁上形成侧壁间隔物。 形成多个第二导电型阱，多个第二导电型阱中的每一个形成在相应的第一导电型阱之间。 在第一导电型阱和第二导电类型阱之间形成多个浅沟槽隔离。 通过第一选择性外延生长工艺形成多个第一导电型阱，并且通过第二选择性外延生长工艺形成多个第二导电型阱。

公开(公告)号：US06713791B2

公开(公告)日：2004-03-30

申请号：US09770788

申请日：2001-01-26

申请人： Louis L. Hsu ,  Rajiv V. Joshi ,  Fariborz Assaderaghi ,  Dan Moy ,  Werner Rausch ,  James Culp

发明人： Louis L. Hsu ,  Rajiv V. Joshi ,  Fariborz Assaderaghi ,  Dan Moy ,  Werner Rausch ,  James Culp

IPC分类号： H01L2974

CPC分类号： H01L27/1027 ,  G11C5/142 ,  G11C11/39

摘要： A T-RAM array having a planar cell structure is presented. The T-RAM array includes n-MOS and p-MOS support devices which are fabricated by sharing process implant steps with T-RAM cells of the T-RAM array. A method is also presented for fabricating the T-RAM array having the planar cell structure. The method entails simultaneously fabricating a first portion of a T-RAM cell and the n-MOS support device; simultaneously fabricating a second portion of the T-RAM cell and the p-MOS support device; and finishing the fabrication of the T-RAM cell by interconnecting the T-RAM cell with the p-MOS and n-MOS support devices. The first portion of the T-RAM cell is a transfer gate and the second portion of the T-RAM cell is a gated-lateral thyristor storage element. Accordingly, process steps in fabricating the T-RAM cells are shared with process steps in fabricating the n-MOS and p-MOS support devices. The n-MOS and p-MOS support devices refer to sense amplifiers, wordline drivers, column and row decoders, etc. which are connected to the T-RAM array.

摘要翻译： 提出了具有平面单元结构的T-RAM阵列。 T-RAM阵列包括通过与T-RAM阵列的T-RAM单元共享处理注入步骤制造的n-MOS和p-MOS支持器件。 还提出了一种制造具有平面单元结构的T-RAM阵列的方法。 该方法需要同时制造T-RAM单元和n-MOS支持器件的第一部分; 同时制造T-RAM单元和p-MOS支持装置的第二部分; 并通过将T-RAM单元与p-MOS和n-MOS支持器件相互连接来完成T-RAM单元的制造。 T-RAM单元的第一部分是传输门，并且T-RAM单元的第二部分是门控侧晶闸管存储元件。 因此，制造T-RAM单元的工艺步骤与制造n-MOS和p-MOS支持器件的工艺步骤共享。 n-MOS和p-MOS支持器件是指连接到T-RAM阵列的读出放大器，字线驱动器，列和行解码器等。

公开(公告)号：US20050106800A1

公开(公告)日：2005-05-19

申请号：US10713447

申请日：2003-11-14

申请人： Wilfried Haensch ,  Terence Hook ,  Louis Hsu ,  Rajiv Joshi ,  Werner Rausch

发明人： Wilfried Haensch ,  Terence Hook ,  Louis Hsu ,  Rajiv Joshi ,  Werner Rausch

IPC分类号： H01L21/76 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L29/78 ,  H01L21/823892 ,  H01L27/0928

摘要： A method for forming a CMOS well structure including forming a plurality of first conductivity type wells over a substrate, each of the plurality of first conductivity type wells formed in a respective opening in a first mask. A cap is formed over each of the first conductivity type wells, and the first mask is removed. Sidewall spacers are formed on sidewalls of each of the first conductivity type wells. A plurality of second conductivity type wells are formed, each of the plurality of second conductivity type wells are formed between respective first conductivity type wells. A plurality of shallow trench isolations are formed between the first conductivity type wells and second conductive type wells. The plurality of first conductivity type wells are formed by a first selective epitaxial growth process, and the plurality of second conductivity type wells are formed by a second selective epitaxial growth process.

摘要翻译： 一种用于形成CMOS阱结构的方法，包括在衬底上形成多个第一导电类型阱，所述多个第一导电类型阱中的每一个形成在第一掩模中的相应开口中。 在每个第一导电类型的阱上形成盖，并且去除第一掩模。 在每个第一导电类型的孔的侧壁上形成侧壁间隔物。 形成多个第二导电型阱，多个第二导电型阱中的每一个形成在相应的第一导电型阱之间。 在第一导电型阱和第二导电类型阱之间形成多个浅沟槽隔离。 通过第一选择性外延生长工艺形成多个第一导电型阱，并且通过第二选择性外延生长工艺形成多个第二导电型阱。

公开(公告)号：US20070045749A1

公开(公告)日：2007-03-01

申请号：US11551959

申请日：2006-10-23

申请人： Wilfried Haensch ,  Terence Hook ,  Louis Hsu ,  Rajiv Joshi ,  Werner Rausch

发明人： Wilfried Haensch ,  Terence Hook ,  Louis Hsu ,  Rajiv Joshi ,  Werner Rausch

IPC分类号： H01L29/76

CPC分类号： H01L29/78 ,  H01L21/823892 ,  H01L27/0928

摘要： A method for forming a CMOS well structure including forming a plurality of first conductivity type wells over a substrate, each of the plurality of first conductivity type wells formed in a respective opening in a first mask. A cap is formed over each of the first conductivity type wells, and the first mask is removed. Sidewall spacers are formed on sidewalls of each of the first conductivity type wells. A plurality of second conductivity type wells are formed, each of the plurality of second conductivity type wells are formed between respective first conductivity type wells. A plurality of shallow trench isolations are formed between the first conductivity type wells and second conductive type wells. The plurality of first conductivity type wells are formed by a first selective epitaxial growth process, and the plurality of second conductivity type wells are formed by a second selective epitaxial growth process.

摘要翻译： 一种用于形成CMOS阱结构的方法，包括在衬底上形成多个第一导电类型阱，所述多个第一导电类型阱中的每一个形成在第一掩模中的相应开口中。 在每个第一导电类型的阱上形成盖，并且去除第一掩模。 在每个第一导电类型的孔的侧壁上形成侧壁间隔物。 形成多个第二导电型阱，多个第二导电型阱中的每一个形成在相应的第一导电型阱之间。 在第一导电型阱和第二导电类型阱之间形成多个浅沟槽隔离。 通过第一选择性外延生长工艺形成多个第一导电型阱，并且通过第二选择性外延生长工艺形成多个第二导电型阱。

公开(公告)号：US20090008705A1

公开(公告)日：2009-01-08

申请号：US11773607

申请日：2007-07-05

申请人： Huilong Zhu ,  Thomas W. Dyer ,  Jack A. Mandelman ,  Werner Rausch

发明人： Huilong Zhu ,  Thomas W. Dyer ,  Jack A. Mandelman ,  Werner Rausch

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7842 ,  H01L29/66795 ,  H01L29/785

摘要： A silicon containing fin is formed on a semiconductor substrate. A silicon oxide layer is formed around the bottom of the silicon containing fin. A gate dielectric is formed on the silicon containing fin followed by formation of a gate electrode. While protecting the portion of the semiconductor fin around the channel, a bottom portion of the silicon containing semiconductor fin is etched by a isotropic etch leaving a body strap between the channel of a finFET on the silicon containing fin and an underlying semiconductor layer underneath the silicon oxide layer. The fin may comprise a stack of inhomogeneous layers in which a bottom layer is etched selectively to a top semiconductor layer. Alternatively, the fin may comprise a homogeneous semiconductor material and the silicon containing fin may be protected by dielectric films on the sidewalls and top surfaces of the silicon containing fin.

摘要翻译： 在半导体衬底上形成含硅翅片。 在含硅翅片的底部周围形成氧化硅层。 在含硅鳍上形成栅电介质，形成栅电极。 在保护半导体翅片周围的通道的部分的同时，通过各向同性的蚀刻蚀刻含硅半导体鳍片的底部部分，从而在含硅鳍片上的finFET的通道和硅下方的下面的半导体层之间留下体带 氧化层。 翅片可以包括不均匀层的堆叠，其中底层被选择性地蚀刻到顶部半导体层。 或者，翅片可以包括均匀的半导体材料，并且含硅翅片可以由含硅翅片的侧壁和顶表面上的电介质膜保护。

公开(公告)号：US07361959B2

公开(公告)日：2008-04-22

申请号：US11164515

申请日：2005-11-28

申请人： Christopher D. Sheraw ,  Alyssa C. Bonnoit ,  K. Paul Muller ,  Werner Rausch

发明人： Christopher D. Sheraw ,  Alyssa C. Bonnoit ,  K. Paul Muller ,  Werner Rausch

IPC分类号： H01L29/76

CPC分类号： H01L27/0629 ,  H01L21/26506 ,  H01L28/20 ,  H01L28/40 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits, as well as methods for forming such CMOS circuits. More specifically, the present invention relates to CMOS circuits that contain passive elements, such as buried resistors, capacitors, diodes, inductors, attenuators, power dividers, and antennas, etc., which are characterized by an end contact resistance of less than 90 ohm-microns. Such a low end resistance can be achieved either by reducing the spacer widths of the passive elements to a range of from about 10 nm to about 30 nm, or by masking the passive elements during a pre-amorphization implantation step, so that the passive elements are essentially free of pre-amorphization implants.

摘要翻译： 本发明涉及互补金属氧化物半导体（CMOS）电路，以及用于形成这种CMOS电路的方法。 更具体地说，本发明涉及包含诸如埋地电阻器，电容器，二极管，电感器，衰减器，功率分配器和天线等无源元件的CMOS电路，其特征在于端接触电阻小于90欧姆 微量元素 这样的低端电阻可以通过将无源元件的间隔物宽度减小到约10nm至约30nm的范围，或通过在预非晶化注入步骤期间掩蔽无源元件来实现，使得无源元件 基本上没有前非晶化植入物。

公开(公告)号：US20060076627A1

公开(公告)日：2006-04-13

申请号：US10711899

申请日：2004-10-12

申请人： Huajie Chen ,  Omer Dokumaci ,  Oleg Gluschenkov ,  Werner Rausch

发明人： Huajie Chen ,  Omer Dokumaci ,  Oleg Gluschenkov ,  Werner Rausch

IPC分类号： H01L29/94

CPC分类号： H01L21/26533 ,  H01L21/02238 ,  H01L21/26513 ,  H01L21/31654 ,  H01L21/31675 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/66636

摘要： A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.

摘要翻译： 形成场效应晶体管的方法产生更浅和更尖的结，同时在与当前制造技术一致的工艺中最大化掺杂剂活化。 更具体地，本发明增加了硅衬底的顶表面的氧含量。 优选在增加硅衬底的顶表面的氧含量之前清洁硅衬底的顶表面。 硅衬底的顶表面的氧含量高于硅衬底的其它部分，但低于防止外延生长的量。 这允许本发明在硅​​衬底的顶表面上外延生长硅层。 此外，增加的氧含量基本上限制外延硅层内的掺杂剂移动到硅衬底中。

公开(公告)号：US20060065914A1

公开(公告)日：2006-03-30

申请号：US10711637

申请日：2004-09-29

申请人： Huajie Chen ,  Dureseti Chidambarrao ,  Sang-Hyun Oh ,  Siddhartha Panda ,  Werner Rausch ,  Tsutomu Sato ,  Henry Utomo

发明人： Huajie Chen ,  Dureseti Chidambarrao ,  Sang-Hyun Oh ,  Siddhartha Panda ,  Werner Rausch ,  Tsutomu Sato ,  Henry Utomo

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/28052 ,  H01L21/28079 ,  H01L21/7624 ,  H01L29/1045 ,  H01L29/165 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A field effect transistor (“FET”) is provided which includes a gate stack overlying a single-crystal semiconductor region of a substrate, a pair of first spacers disposed over sidewalls of said gate stack, and a pair of regions consisting essentially of a single-crystal semiconductor alloy which are disposed on opposite sides of the gate stack. Each of the semiconductor alloy regions is spaced a first distance from the gate stack. The source region and drain region of the FET are at least partly disposed in respective ones of the semiconductor alloy regions, such that the source region and the drain region are each spaced a second distance from the gate stack by a first spacer of the pair of first spacers, the second distance being different from the first distance.

公开(公告)号：US20050054169A1

公开(公告)日：2005-03-10

申请号：US10605100

申请日：2003-09-09

申请人： Tina Wagner ,  Werner Rausch ,  Sadanand Deshpande

发明人： Tina Wagner ,  Werner Rausch ,  Sadanand Deshpande

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L21/331

CPC分类号： H01L29/66772 ,  H01L29/78618

摘要： A method is provided for forming an SOI MOSFET device with a silicon layer formed on a dielectric layer with a gate electrode stack, with sidewall spacers on sidewalls of the gate electrode stack and raised source/drain regions formed on the surface of the silicon layer. The gate electrode stack comprises a gate electrode formed of polysilicon over a gate dielectric layer formed on the surface of the silicon layer. A plug of dielectric material is formed in a notch in a cap layer above the gate polysilicon. The sidewalls of the gate electrode is covered by the sidewall spacers which cover a portion of the plug for the purpose of eliminating the exposure of the gate polysilicon so that formation of spurious epitaxial growth during the formation of raised source/drain regions is avoided.

摘要翻译： 提供了一种用于形成具有形成在具有栅极电极堆叠的电介质层上的硅层的SOI MOSFET器件的方法，在栅电极堆叠的侧壁上具有侧壁间隔物，并且形成在硅层的表面上的升高的源极/漏极区域。 栅极电极堆叠包括在形成于硅层的表面上的栅极电介质层上的多晶硅形成的栅电极。 在栅多晶硅上方的帽层中的凹口中形成介电材料塞。 为了消除栅极多晶硅的暴露，覆盖一部分插塞的侧壁间隔物覆盖栅电极的侧壁，从而避免在形成升高的源极/漏极区域期间形成假外延生长。