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    Method system and apparatus for instruction execution tracing with out of order processors
    3.
    发明授权
    Method system and apparatus for instruction execution tracing with out of order processors 失效
    无序处理器的指令执行跟踪方法系统和装置

    公开(公告)号：US06681321B1

    公开(公告)日：2004-01-20

    申请号：US09552856

    申请日：2000-04-20

    申请人： Jason N. Dale ,  Jim A. Kahle ,  Douglas R. Logan ,  Alex E. Mericas ,  William J. Starke ,  Philip L. Vitale

    发明人： Jason N. Dale ,  Jim A. Kahle ,  Douglas R. Logan ,  Alex E. Mericas ,  William J. Starke ,  Philip L. Vitale

    IPC分类号： G06F1100

    CPC分类号： G06F11/3636

    摘要： A method, system and apparatus for instruction execution tracing with out of order speculative processors. Information corresponding to the state of an instruction cache and a data cache is stored in a trace storage device along with information corresponding to instructions sequenced and executed by the processor. When a cache load is necessary, updated cache information is stored in the trace storage device. Thereby, the state of the cache at all times during execution of instructions may be known from the information stored in the trace storage device. Additionally, the particular instructions sequenced and executed is known from the sequenced instructions information and the executed instructions information stored in the trace storage device. Hence the instruction execution stream may be reconstructed from the information stored in the trace storage device.

    摘要翻译： 用于无序推测处理器的指令执行跟踪的方法，系统和装置。 与指令高速缓存和数据高速缓存的状态相对应的信息与跟随由处理器排序并执行的指令对应的信息一起存储在跟踪存储设备中。 当需要缓存加载时，更新的缓存信息被存储在跟踪存储设备中。 因此，可以从存储在跟踪存储装置中的信息中知道执行指令期间的所有时间的高速缓存的状态。 此外，根据存储在跟踪存储设备中的排序指令信息和执行的指令信息，已知排序并执行的特定指令。 因此，可以从存储在跟踪存储设备中的信息重建指令执行流。

    Floating point operaton throughput control
    5.
    发明授权
    Floating point operaton throughput control 失效
    浮点运算吞吐量控制

    公开(公告)号：US5623616A

    公开(公告)日：1997-04-22

    申请号：US327130

    申请日：1994-10-20

    申请人： Philip L. Vitale ,  William L. Walker

    发明人： Philip L. Vitale ,  William L. Walker

    IPC分类号： G06F9/38 ,  G06F9/30

    CPC分类号： G06F9/3873 ,  G06F9/3836 ,  G06F9/3869

    摘要： A circuit and method degrades throughput of floating point operations within a computing system. At the time of manufacture a preprogrammed value is stored. This may be done, for example, using fusible links, separate metal layers, internal bonding pad selection, EPROM/OTP memory cells, ion milling, laser evaporation and external programming pins. When a floating point processor processes a floating point operation, operation of a main processor is delayed an amount corresponding to the preprogrammed value. For example, when the floating point processor processes a floating point operation, a counter begins to count. Operation of the main processor is delayed until the counter has counted to a number equal to the preprogrammed value. Upon the counter completing counting to a number equal to the preprogrammed value, normal operation of the main processor is resumed.

    摘要翻译： 电路和方法降低计算系统内浮点运算的吞吐量。 在制造时存储预编程值。 这可以例如使用熔丝，单独的金属层，内部焊盘选择，EPROM / OTP存储单元，离子铣削，激光蒸发和外部编程引脚来完成。 当浮点处理器处理浮点操作时，主处理器的操作被延迟与预编程值对应的量。 例如，当浮点处理器处理浮点运算时，计数器开始计数。 主处理器的操作被延迟，直到计数器计数到等于预编程值的数字。 当计数器完成计数到等于预编程值的数字时，恢复主处理器的正常操作。

    Weighted-region cycle accounting for multi-threaded processor cores
    7.
    发明授权
    Weighted-region cycle accounting for multi-threaded processor cores 失效
    加权区域循环计算多线程处理器内核

    公开(公告)号：US08161493B2

    公开(公告)日：2012-04-17

    申请号：US12173771

    申请日：2008-07-15

    申请人： Michael S. Floyd ,  Steven R. Kunkel ,  Aaron C. Sawdey ,  Philip L. Vitale

    发明人： Michael S. Floyd ,  Steven R. Kunkel ,  Aaron C. Sawdey ,  Philip L. Vitale

    IPC分类号： G06F9/45 ,  G06F9/46

    CPC分类号： G06F9/3851 ,  G06F11/3409 ,  G06F11/3466 ,  G06F2201/88

    摘要： An aspect of the present invention improves the accuracy of measuring processor utilization of multi-threaded cores by providing a calibration facility that derives utilization in the context of the overall dynamic operating state of the core by assigning weights to idle threads and assigning weights to run threads, depending on the status of the core. From previous chip designs it has been established in a Simultaneous Multi Thread (SMT) core that not all idle cycles in a hardware thread can be equally converted into useful work. Competition for core resources reduces the conversion efficiency of one thread's idle cycles when any other thread is running on the same core.

    摘要翻译： 本发明的一个方面通过提供一种校准设备来提高测量多线程核心处理器利用率的准确性，该校准设备通过向空闲线程分配权重并为运行线程分配权重而在核心的整体动态操作状态的上下文中获得利用 ，取决于核心的状态。 从先前的芯片设计，已经建立在同步多线程（SMT）核心中，并非硬件线程中的所有空闲周期都可以平等地转换为有用的工作。 核心资源的竞争降低了一个线程在同一个核心上运行的一个线程的空闲周期的转换效率。

    DEVICE FOR AND METHOD OF WEIGHTED-REGION CYCLE ACCOUNTING FOR MULTI-THREADED PROCESSOR CORES
    8.
    发明申请
    DEVICE FOR AND METHOD OF WEIGHTED-REGION CYCLE ACCOUNTING FOR MULTI-THREADED PROCESSOR CORES 失效
    用于多线加工器的加权区域循环会计的装置和方法

    公开(公告)号：US20100287561A1

    公开(公告)日：2010-11-11

    申请号：US12173771

    申请日：2008-07-15

    申请人： Michael S. Floyd ,  Steven R. Kunkel ,  Aaron C. Sawdey ,  Philip L. Vitale

    发明人： Michael S. Floyd ,  Steven R. Kunkel ,  Aaron C. Sawdey ,  Philip L. Vitale

    IPC分类号： G06F9/46

    CPC分类号： G06F9/3851 ,  G06F11/3409 ,  G06F11/3466 ,  G06F2201/88

    摘要： An aspect of the present invention improves the accuracy of measuring processor utilization of multi-threaded cores by providing a calibration facility that derives utilization in the context of the overall dynamic operating state of the core by assigning weights to idle threads and assigning weights to run threads, depending on the status of the core. From previous chip designs it has been established in a Simultaneous Multi Thread (SMT) core that not all idle cycles in a hardware thread can be equally converted into useful work. Competition for core resources reduces the conversion efficiency of one thread's idle cycles when any other thread is running on the same core.

    摘要翻译： 本发明的一个方面通过提供一种校准设备来提高测量多线程核心处理器利用率的准确性，该校准设备通过向空闲线程分配权重并为运行线程分配权重而在核心的整体动态操作状态的上下文中获得利用 ，取决于核心的状态。 从先前的芯片设计，已经建立在同步多线程（SMT）核心中，并非硬件线程中的所有空闲周期都可以平等地转换为有用的工作。 核心资源的竞争降低了一个线程在同一个核心上运行的一个线程的空闲周期的转换效率。