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公开(公告)号：US08615689B2
公开(公告)日：2013-12-24
申请号：US13612396
申请日：2012-09-12
IPC分类号： G11C29/00
CPC分类号： G11B27/107 , G11B27/24 , G11B27/36 , G11B2220/93
摘要： A method for longitudinal position (LPOS) detection in a magnetic tape storage system for storing data upon linear tape open (LTO) magnetic storage tape, which data includes odd and even 36-bit LPOS words with error correcting ability. The method includes first encoding positional information onto the tape within the 36-bit LPOS words using each LPOS word's 8-bit sync mark field, and six of each LPOS word's 4-bit symbol fields, wherein 6 of 24 total bits comprise the encoded 8-bit sync mark field: Sy, and six 4-bit symbol fields are utilized as parity bits. The magnetic tape storage system passes the LTO magnetic storage tape encoded with the odd and even LPOS words with error correcting ability longitudinally across a servo reader/writer at a known speed, decoding the encoded positional information and detecting and correcting both ambiguous bits and single erroneous bit errors.
摘要翻译： 一种用于在线性磁带打开（LTO）磁存储磁带上存储数据的磁带存储系统中的纵向位置（LPOS）检测方法，该数据包括具有纠错能力的奇数和偶数36位LPOS字。 该方法包括使用每个LPOS字的8位同步标记字段以及每个LPOS字的4位符号字段中的六个，在36位LPOS字中的位置信息之上编码位置信息，其中24个总比特中的6个包括编码的8 位同步标记字段：Sy和六个4位符号字段用作奇偶校验位。 磁带存储系统以已知速度将穿过伺服读取器/写入器的具有纠错能力的奇数和偶数LPOS字编码的LTO磁存储带纵向跨越伺服读取器/写入器，对编码的位置信息进行解码，并检测和校正两个不明确的位和单个错误 位错误。
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公开(公告)号：US20130003213A1
公开(公告)日：2013-01-03
申请号：US13612396
申请日：2012-09-12
CPC分类号： G11B27/107 , G11B27/24 , G11B27/36 , G11B2220/93
摘要： A method for longitudinal position (LPOS) detection in a magnetic tape storage system for storing data upon linear tape open (LTO) magnetic storage tape, which data includes odd and even 36-bit LPOS words with error correcting ability. The method includes first encoding positional information onto the tape within the 36-bit LPOS words using each LPOS word's 8-bit sync mark field, and six of each LPOS word's 4-bit symbol fields, wherein 6 of 24 total bits comprise the encoded 8-bit sync mark field: Sy, and six 4-bit symbol fields are utilized as parity bits. The magnetic tape storage system passes the LTO magnetic storage tape encoded with the odd and even LPOS words with error correcting ability longitudinally across a servo reader/writer at a known speed, decoding the encoded positional information and detecting and correcting both ambiguous bits and single erroneous bit errors.
摘要翻译： 一种用于在线性磁带打开（LTO）磁存储磁带上存储数据的磁带存储系统中的纵向位置（LPOS）检测方法，该数据包括具有纠错能力的奇数和偶数36位LPOS字。 该方法包括使用每个LPOS字的8位同步标记字段以及每个LPOS字的4位符号字段中的六个，在36位LPOS字中的位置信息之上编码位置信息，其中24个总比特中的6个包括编码的8 位同步标记字段：Sy和六个4位符号字段用作奇偶校验位。 磁带存储系统以已知速度将穿过伺服读取器/写入器的具有纠错能力的奇数和偶数LPOS字编码的LTO磁存储带纵向跨越伺服读取器/写入器，对编码的位置信息进行解码，并检测和校正两个不明确的位和单个错误 位错误。
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公开(公告)号：US08271857B2
公开(公告)日：2012-09-18
申请号：US12119975
申请日：2008-05-13
IPC分类号： G11C29/00
CPC分类号： G11B27/107 , G11B27/24 , G11B27/36 , G11B2220/93
摘要： The invention includes a method for longitudinal position (LPOS) detection in a magnetic tape storage system for storing data upon linear tape open (LTO) magnetic storage tape, which data includes odd and even 36-bit LPOS words with error correcting ability. The method includes steps of encoding positional information onto the magnetic storage tape within the odd and even 36-bit LPOS words using each LPOS word's 8-bit sync mark field, Sy, and six of each LPOS word's 4-bit symbol fields, L0, L1, L2 L3, L4, and L5, wherein 6 of 24 total bits comprising the encoded 8-bit sync mark field: Sy, and six 4-bit symbol fields: L0, L1, L2 L3, L4, and L5 are utilized as parity bits, operating the magnetic tape storage system by passing the LTO magnetic storage tape encoded with the odd and even LPOS words with error correcting ability longitudinally across a servo reader/writer at a known speed, decoding the encoded positional information by reading either two words sequentially or two words simultaneously, the simultaneous reading requiring that the LPOS words include servo band numbers and detecting and correcting both ambiguous bits and single erroneous bit errors.
摘要翻译： 本发明包括一种用于在线性磁带打开（LTO）磁存储磁带上存储数据的磁带存储系统中的纵向位置（LPOS）检测方法，该数据包括具有纠错能力的奇数和偶数的36位LPOS字。 该方法包括使用每个LPOS字的8位同步标记字段Sy和每个LPOS字的4位符号字段L0中的6个将位置信息编码到奇数和偶数36位LPOS字中的位置信息的步骤， L1，L2 L3，L4和L5，其中包括编码的8位同步标记字段Sy的24个总比特中的6个和6个4位符号字段：L0，L1，L2 L3，L4和L5用作 奇偶校验位，通过以已知速度通过伺服读取器/写入器将具有纠错能力的奇数和偶数LPOS字编码的LTO磁存储带纵向跨越伺服读取器/写入器来操作磁带存储系统，通过读取两个字来解码编码的位置信息 同时读取，要求LPOS字包括伺服频带号，并且检测和校正两个不明确的位和单个错误位错误。
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公开(公告)号：US20090287982A1
公开(公告)日：2009-11-19
申请号：US12119975
申请日：2008-05-13
CPC分类号： G11B27/107 , G11B27/24 , G11B27/36 , G11B2220/93
摘要： The invention includes a method for longitudinal position (LPOS) detection in a magnetic tape storage system for storing data upon linear tape open (LTO) magnetic storage tape, which data includes odd and even 36-bit LPOS words with error correcting ability. The method includes steps of encoding positional information onto the magnetic storage tape within the odd and even 36-bit LPOS words using each LPOS word's 8-bit sync mark field, Sy, and six of each LPOS word's 4-bit symbol fields, L0, L1, L2 L3, L4, and L5, wherein 6 of 24 total bits comprising the encoded 8-bit sync mark field: Sy, and six 4-bit symbol fields: L0, L1, L2 L3, L4, and L5 are utilized as parity bits, operating the magnetic tape storage system by passing the LTO magnetic storage tape encoded with the odd and even LPOS words with error correcting ability longitudinally across a servo reader/writer at a known speed, decoding the encoded positional information by reading either two words sequentially or two words simultaneously, the simultaneous reading requiring that the LPOS words include servo band numbers and detecting and correcting both ambiguous bits and single erroneous bit errors.
摘要翻译： 本发明包括一种用于在线性磁带打开（LTO）磁存储磁带上存储数据的磁带存储系统中的纵向位置（LPOS）检测方法，该数据包括具有纠错能力的奇数和偶数的36位LPOS字。 该方法包括使用每个LPOS字的8位同步标记字段Sy和每个LPOS字的4位符号字段L0中的6个将位置信息编码到奇数和偶数36位LPOS字中的位置信息的步骤， L1，L2 L3，L4和L5，其中包括编码的8位同步标记字段Sy的24个总比特中的6个和6个4位符号字段：L0，L1，L2 L3，L4和L5用作 奇偶校验位，通过以已知速度通过伺服读取器/写入器将具有纠错能力的奇数和偶数LPOS字编码的LTO磁存储带纵向跨越伺服读取器/写入器来操作磁带存储系统，通过读取两个字来解码编码的位置信息 同时读取，要求LPOS字包括伺服频带号，并且检测和校正两个不明确的位和单个错误位错误。
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公开(公告)号：US08171377B2
公开(公告)日：2012-05-01
申请号：US12023374
申请日：2008-01-31
IPC分类号： G11C29/00
CPC分类号： H03M13/1545 , G06F11/1044 , H03M13/1515
摘要： A system to improve memory reliability in computer systems that may include memory chips, and may rely on a error control encoder to send codeword symbols for storage in each of the memory chips. At least two symbols from a codeword are assigned to each memory chip and therefore failure of any of the memory chips could affect two symbols or more. The system may also include a table to record failures and partial failures of the codeword symbols for each of the memory chips so the error control encoder can correct subsequent partial failures based upon the previous partial failures. The error control coder is capable of correcting and/or detecting more errors if only a fraction of a chip is noted in the table as having a failure as opposed to a full chip noted as having a failure.
摘要翻译： 一种用于提高可能包括存储器芯片的计算机系统中的存储器可靠性的系统，并且可以依赖于错误控制编码器来发送用于存储在每个存储器芯片中的码字符号。 来自码字的至少两个符号被分配给每个存储器芯片，因此任何存储器芯片的故障可能影响两个或更多个符号。 该系统还可以包括用于记录每个存储器芯片的码字符号的故障和部分故障的表，因此错误控制编码器可以基于先前的部分故障来校正随后的部分故障。 误差控制编码器能够校正和/或检测更多的误差，如果在表中只有一部分芯片被注意为具有故障，而不是被称为具有故障的全芯片。
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公开(公告)号：US09128868B2
公开(公告)日：2015-09-08
申请号：US12023356
申请日：2008-01-31
申请人： Luis A. Lastras-Montano , Piyush C. Patel , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd
发明人： Luis A. Lastras-Montano , Piyush C. Patel , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd
CPC分类号： G06F11/1044 , G06F11/08 , G06F11/14 , H04W4/00 , H04W28/04
摘要： A system to improve error code decoding with retries may include a processing unit that requests data packets, and a queue to hold the data packets for the processing unit. The system may also include a decoder to determine a processing time for each data packet in the queue based upon any errors in each data packet, and if the processing time for a particular data packet is greater than a threshold, then to renew any requests for the data packets that are in the queue.
摘要翻译： 通过重试来改进错误代码解码的系统可以包括请求数据分组的处理单元和用于保存用于处理单元的数据分组的队列。 系统还可以包括解码器，用于基于每个数据分组中的任何错误来确定队列中每个数据分组的处理时间，并且如果特定数据分组的处理时间大于阈值，则更新对于 队列中的数据包。
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公开(公告)号：US20130198705A1
公开(公告)日：2013-08-01
申请号：US13360083
申请日：2012-01-27
申请人： Gradus (Geert) Janssen , Luis Lastras-Montano , Alexey Y. Lvov , Viresh Paruthi , Robert Shadowen , Barry M. Trager , Shmuel Winograd , Ali El-Zein
发明人： Gradus (Geert) Janssen , Luis Lastras-Montano , Alexey Y. Lvov , Viresh Paruthi , Robert Shadowen , Barry M. Trager , Shmuel Winograd , Ali El-Zein
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： In one exemplary embodiment of the invention, a method includes: receiving a first description for a circuit whose operation over a plurality of inputs is to be verified; receiving a second description for expected behavior of the circuit, where the expected behavior in the second description is expressed as a set of algebraic systems of multivariable polynomials over at least one Galois field; applying at least one computational algebraic geometry technique to a combination of the first description and the second description to determine whether the circuit is verified, where verification of the circuit confirms that at least one output obtained based on the first description corresponds to at least one expected value based on the expected behavior expressed in the second description; and outputting an indication as to whether the circuit is verified.
摘要翻译： 在本发明的一个示例性实施例中，一种方法包括：接收对要对其进行验证的多个输入的操作的电路的第一描述; 接收对所述电路的预期行为的第二描述，其中所述第二描述中的预期行为被表示为在至少一个伽罗瓦域上的多变量多项式的代数系统集合; 将至少一个计算代数几何技术应用于第一描述和第二描述的组合以确定电路是否被验证，其中电路的验证确认基于第一描述获得的至少一个输出对应于至少一个预期的 基于在第二描述中表达的预期行为的价值; 并且输出关于电路是否被验证的指示。
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公开(公告)号：US08352806B2
公开(公告)日：2013-01-08
申请号：US12023498
申请日：2008-01-31
申请人： Marc A. Gollub , Luis A. Lastras-Montano , Piyush C. Patel , Eric E. Retter , Barry M. Trager , Shmuel Winograd , Kenneth L. Wright
发明人： Marc A. Gollub , Luis A. Lastras-Montano , Piyush C. Patel , Eric E. Retter , Barry M. Trager , Shmuel Winograd , Kenneth L. Wright
IPC分类号： G06F11/00
CPC分类号： H03M13/1545 , G06F11/1048 , H03M13/1515 , H03M13/154 , H03M13/353 , H03M13/3707 , H03M13/6511
摘要： A system to improve memory failure management may include memory, and an error control decoder to determine failures in the memory. The system may also include an agent that may monitor failures in the memory. The system may further include a table where the error control decoder may record the failures, and where the agent can read and write to.
摘要翻译： 改善存储器故障管理的系统可以包括存储器和用于确定存储器中的故障的错误控制解码器。 系统还可以包括可以监视存储器中的故障的代理。 该系统还可以包括一个表，其中错误控制解码器可以记录故障，以及代理可以在哪里读写。
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9.发明授权System to improve miscorrection rates in error control code through buffering and associated methods 失效系统通过缓冲和相关方法提高错误控制代码中的错误率公开(公告)号：US08176391B2
公开(公告)日：2012-05-08
申请号：US12023516
申请日：2008-01-31
申请人： Irving G. Baysah , Timothy J. Dell , Luis A. Lastras-Montano , Warren E. Maule , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd , Kenneth L. Wright
发明人： Irving G. Baysah , Timothy J. Dell , Luis A. Lastras-Montano , Warren E. Maule , Eric E. Retter , Barry M. Trager , Michael R. Trombley , Shmuel Winograd , Kenneth L. Wright
IPC分类号： H03M13/00
CPC分类号： G06F11/1044
摘要： A system to improve miscorrection rates in error control code may include an error control decoder with a safe decoding mode that processes at least two data packets. The system may also include a buffer to receive the processed at least two data packets from the error control decoder. The error control decoder may apply a logic OR operation to the uncorrectable error signal related to the processing of the at least two data packets to produce a global uncorrectable error signal. The system may further include a recipient to receive the at least two data packets and the global uncorrectable error signal.
摘要翻译： 用于改善错误控制代码中的错误率的系统可以包括处理至少两个数据分组的具有安全解码模式的错误控制解码器。 系统还可以包括缓冲器，以从误差控制解码器接收经处理的至少两个数据分组。 误差控制解码器可以对与至少两个数据分组的处理相关的不可校正误差信号应用逻辑或运算，以产生全局不可校正的误差信号。 系统还可以包括接收器以接收至少两个数据分组和全局不可校正的误差信号。
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公开(公告)号：US08640065B2
公开(公告)日：2014-01-28
申请号：US13360083
申请日：2012-01-27
申请人： Gradus (Geert) Janssen , Luis Lastras-Montano , Alexey Y. Lvov , Viresh Paruthi , Robert Shadowen , Barry M. Trager , Shmuel Winograd , Ali El-Zein
发明人： Gradus (Geert) Janssen , Luis Lastras-Montano , Alexey Y. Lvov , Viresh Paruthi , Robert Shadowen , Barry M. Trager , Shmuel Winograd , Ali El-Zein
CPC分类号： G06F17/504
摘要： In one exemplary embodiment of the invention, a method includes: receiving a first description for a circuit whose operation over a plurality of inputs is to be verified; receiving a second description for expected behavior of the circuit, where the expected behavior in the second description is expressed as a set of algebraic systems of multivariable polynomials over at least one Galois field; applying at least one computational algebraic geometry technique to a combination of the first description and the second description to determine whether the circuit is verified, where verification of the circuit confirms that at least one output obtained based on the first description corresponds to at least one expected value based on the expected behavior expressed in the second description; and outputting an indication as to whether the circuit is verified.
摘要翻译： 在本发明的一个示例性实施例中，一种方法包括：接收对要对其进行验证的多个输入的操作的电路的第一描述; 接收对所述电路的预期行为的第二描述，其中所述第二描述中的预期行为被表示为在至少一个伽罗瓦域上的多变量多项式的代数系统集合; 将至少一个计算代数几何技术应用于第一描述和第二描述的组合以确定电路是否被验证，其中电路的验证确认基于第一描述获得的至少一个输出对应于至少一个预期的 基于在第二描述中表达的预期行为的价值; 并且输出关于电路是否被验证的指示。
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