公开(公告)号：US20090144737A1

公开(公告)日：2009-06-04

申请号：US12358405

申请日：2009-01-23

申请人： William Joseph Armstrong ,  Bruce G. Mealey ,  Naresh Nayar ,  Balaram Sinharoy

发明人： William Joseph Armstrong ,  Bruce G. Mealey ,  Naresh Nayar ,  Balaram Sinharoy

IPC分类号： G06F9/44 ,  G06F9/38

CPC分类号： G06F9/4812 ,  G06F9/30189 ,  G06F9/3851 ,  G06F9/485

摘要： An apparatus and program product utilize a multithreaded processor having at least one hardware thread among a plurality of hardware threads that is capable of being selectively activated and deactivated responsive to a control circuit. The control circuit additionally provides the capability of controlling how an inactive thread can be activated after the thread has been deactivated, e.g., by enabling or disabling reactivation in response to an interrupt.

摘要翻译： 一种装置和程序产品利用多线程处理器，其具有能够响应于控制电路选择性地激活和去激活的多个硬件线程中的至少一个硬件线程。 控制电路另外提供了控制如何在线程被去激活之后如何激活非活动线程的能力，例如通过启用或禁用响应于中断的重新激活。

公开(公告)号：US07496915B2

公开(公告)日：2009-02-24

申请号：US10422682

申请日：2003-04-24

申请人： William Joseph Armstrong ,  Bruce G. Mealey ,  Naresh Nayar ,  Balaram Sinharoy

发明人： William Joseph Armstrong ,  Bruce G. Mealey ,  Naresh Nayar ,  Balaram Sinharoy

IPC分类号： G06F9/46 ,  G06F11/00 ,  G06F1/00 ,  G05B15/00 ,  G05B11/01 ,  G05B13/02

CPC分类号： G06F9/4812 ,  G06F9/30189 ,  G06F9/3851 ,  G06F9/485

摘要： A method utilizes a multithreaded processor having at least one hardware thread among a plurality of hardware threads that is capable of being selectively activated and deactivated responsive to a control circuit. The control circuit additionally provides the capability of controlling how an inactive thread can be activated after the thread has been deactivated, e.g., by enabling or disabling reactivation in response to an interrupt.

摘要翻译： 一种方法利用多线程处理器，其具有多个硬件线程中的至少一个硬件线程，其能够响应于控制电路被选择性地激活和去激活。 控制电路另外提供了控制如何在线程被去激活之后如何激活非活动线程的能力，例如通过启用或禁用响应于中断的重新激活。

公开(公告)号：US08458709B2

公开(公告)日：2013-06-04

申请号：US12358405

申请日：2009-01-23

申请人： William Joseph Armstrong ,  Bruce G. Mealey ,  Naresh Nayar ,  Balaram Sinharoy

发明人： William Joseph Armstrong ,  Bruce G. Mealey ,  Naresh Nayar ,  Balaram Sinharoy

IPC分类号： G06F9/46 ,  G06F15/00

CPC分类号： G06F9/4812 ,  G06F9/30189 ,  G06F9/3851 ,  G06F9/485

摘要： An apparatus and program product utilize a multithreaded processor having at least one hardware thread among a plurality of hardware threads that is capable of being selectively activated and deactivated responsive to a control circuit. The control circuit additionally provides the capability of controlling how an inactive thread can be activated after the thread has been deactivated, e.g., by enabling or disabling reactivation in response to an interrupt.

摘要翻译： 一种装置和程序产品利用多线程处理器，其具有能够响应于控制电路选择性地激活和去激活的多个硬件线程中的至少一个硬件线程。 控制电路另外提供了控制如何在线程被去激活之后如何激活非活动线程的能力，例如通过启用或禁用响应于中断的重新激活。

公开(公告)号：US07484062B2

公开(公告)日：2009-01-27

申请号：US11316070

申请日：2005-12-22

申请人： Ravi K. Arimilli ,  Rama K. Govindaraju ,  Peter H. Hochschild ,  Bruce G. Mealey ,  Satya P. Sharma ,  Balaram Sinharoy

发明人： Ravi K. Arimilli ,  Rama K. Govindaraju ,  Peter H. Hochschild ,  Bruce G. Mealey ,  Satya P. Sharma ,  Balaram Sinharoy

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F9/30032 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/383 ,  G06F9/3834 ,  G06F12/0862 ,  G06F12/0888 ,  G06F12/0897 ,  G06F2212/6028

摘要： A system, method, and a computer readable for inserting data into a cache memory based on information in a semi-synchronous memory copy instruction are disclosed. The method comprises determining a start of a semi-synchronous memory copy operation. The semi-synchronous memory copy operation is checked for a given value in at least one cache injection bit. In response to the given value in the cache injection bit, a predefined number of lines of destination data is copied into at least one level of cache memory.

摘要翻译： 公开了一种基于半同步存储器复制指令中的信息将数据插入高速缓冲存储器的系统，方法和计算机。 该方法包括确定半同步存储器复制操作的开始。 在至少一个高速缓存注入位中检查给定值的半同步存储器复制操作。 响应于高速缓存注入位中的给定值，预定数量的目的地数据行被复制到至少一级的高速缓存存储器中。

公开(公告)号：US07454585B2

公开(公告)日：2008-11-18

申请号：US11316663

申请日：2005-12-22

申请人： Ravi K. Arimilli ,  Rama K. Govindaraju ,  Peter H. Hochschild ,  Bruce G. Mealey ,  Satya P. Sharma ,  Balaram Sinharoy

发明人： Ravi K. Arimilli ,  Rama K. Govindaraju ,  Peter H. Hochschild ,  Bruce G. Mealey ,  Satya P. Sharma ,  Balaram Sinharoy

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F9/3834 ,  G06F9/3004 ,  G06F9/3824

摘要： A system, method, and computer program product for semi-synchronously copying data from a first portion of memory to a second portion of memory are disclosed. The method comprises receiving, in a processor, a call for a semi-synchronous memory copy operation. The semi-synchronous memory copy operation preserves temporal persistence of validity for a virtual source address corresponding to a source location in a memory and a virtual target address corresponding to a target location in the memory by setting a flag bit. The call includes at least the virtual source address, the virtual target address, and an indicator identifying a number of bytes to be copied. The memory copy operation is placed in a queue for execution by a memory controller. The queue is coupled to the memory controller. At least one subsequent instruction is continued to be executed as the subsequent instruction becomes available from an instruction pipeline.

摘要翻译： 公开了一种用于将数据从存储器的第一部分半数同步地复制到存储器的第二部分的系统，方法和计算机程序产品。 该方法包括在处理器中接收对半同步存储器复制操作的呼叫。 半同步存储器复制操作通过设置标志位来保持对应于存储器中的源位置的虚拟源地址和对应于存储器中的目标位置的虚拟目标地址的有效性的时间持续性。 该呼叫至少包括虚拟源地址，虚拟目标地址和标识要复制的字节数的指示符。 存储器复制操作被放置在队列中以由存储器控制器执行。 队列耦合到存储器控制器。 随着随后的指令从指令流水线可用，继续执行至少一个后续指令。

公开(公告)号：US07890703B2

公开(公告)日：2011-02-15

申请号：US12359565

申请日：2009-01-26

申请人： Ravi K. Arimilli ,  Rama K. Govindaraju ,  Peter H. Hochschild ,  Bruce G. Mealey ,  Satya P. Sharma ,  Balaram Sinharoy

发明人： Ravi K. Arimilli ,  Rama K. Govindaraju ,  Peter H. Hochschild ,  Bruce G. Mealey ,  Satya P. Sharma ,  Balaram Sinharoy

IPC分类号： G06F12/02 ,  G06F12/08

CPC分类号： G06F9/30032 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/383 ,  G06F9/3834 ,  G06F12/0862 ,  G06F12/0888 ,  G06F12/0897 ,  G06F2212/6028

摘要： A system, method, and a computer readable for inserting data into a cache memory based on information in a semi-synchronous memory copy instruction are disclosed. The method comprises determining a start of a semi-synchronous memory copy operation. The semi-synchronous memory copy operation is checked for a given value in at least one cache injection bit. In response to the given value in the cache injection bit, a predefined number of lines of destination data is copied into at least one level of cache memory.

摘要翻译： 公开了一种基于半同步存储器复制指令中的信息将数据插入高速缓冲存储器的系统，方法和计算机。 该方法包括确定半同步存储器复制操作的开始。 在至少一个高速缓存注入位中检查给定值的半同步存储器复制操作。 响应于高速缓存注入位中的给定值，预定数量的目的地数据行被复制到至少一级的高速缓存存储器中。

公开(公告)号：US07882321B2

公开(公告)日：2011-02-01

申请号：US12402904

申请日：2009-03-12

申请人： Ravi K. Arimilli ,  Rama K. Govindaraju ,  Peter H. Hochschild ,  Bruce G. Mealey ,  Satya P. Sharma ,  Balaram Sinharoy

发明人： Ravi K. Arimilli ,  Rama K. Govindaraju ,  Peter H. Hochschild ,  Bruce G. Mealey ,  Satya P. Sharma ,  Balaram Sinharoy

IPC分类号： G06F12/02

CPC分类号： G06F12/1441 ,  G06F12/0888 ,  G06F12/0897

摘要： A system, method, and a computer readable for protecting content of a memory page are disclosed. The method includes determining a start of a semi-synchronous memory copy operation. A range of addresses is determined where the semi-synchronous memory copy operation is being performed. An issued instruction that removes a page table entry is detected. The method further includes determining whether the issued instruction is destined to remove a page table entry associated with at least one address in the range of addresses. In response to the issued instruction being destined to remove the page table entry, the execution of the issued instruction is stalled until the semi-synchronous memory copy operation is completed.

摘要翻译： 公开了一种用于保护存储器页面的内容的系统，方法和可读取的计算机。 该方法包括确定半同步存储器复制操作的开始。 确定正在执行半同步存储器复制操作的地址范围。 检测到发出的删除页表条目的指令。 所述方法还包括确定所发出的指令是否旨在去除与地址范围中的至少一个地址相关联的页表条目。 响应于发出的指令旨在去除页表条目，所发出的指令的执行停止，直到半同步存储器复制操作完成。

公开(公告)号：US07506132B2

公开(公告)日：2009-03-17

申请号：US11315757

申请日：2005-12-22

申请人： Ravi K. Arimilli ,  Rama K. Govindaraju ,  Peter H. Hochschild ,  Bruce G. Mealey ,  Satya P. Sharma ,  Balaram Sinharoy

发明人： Ravi K. Arimilli ,  Rama K. Govindaraju ,  Peter H. Hochschild ,  Bruce G. Mealey ,  Satya P. Sharma ,  Balaram Sinharoy

IPC分类号： G06F12/00

CPC分类号： G06F12/1441 ,  G06F12/0888 ,  G06F12/0897

摘要： A system, method, and a computer readable for protecting content of a memory page are disclosed. The method includes determining a start of a semi-synchronous memory copy operation. A range of addresses is determined where the semi-synchronous memory copy operation is being performed. An issued instruction that removes a page table entry is detected. The method further includes determining whether the issued instruction is destined to remove a page table entry associated with at least one address in the range of addresses. In response to the issued instruction being destined to remove the page table entry, the execution of the issued instruction is stalled until the semi-synchronous memory copy operation is completed.

摘要翻译： 公开了一种用于保护存储器页面的内容的系统，方法和可读取的计算机。 该方法包括确定半同步存储器复制操作的开始。 确定正在执行半同步存储器复制操作的地址范围。 检测到发出的删除页表条目的指令。 所述方法还包括确定所发出的指令是否旨在去除与地址范围中的至少一个地址相关联的页表条目。 响应于发出的指令旨在去除页表条目，所发出的指令的执行停止，直到半同步存储器复制操作完成。

公开(公告)号：US20080307182A1

公开(公告)日：2008-12-11

申请号：US12191655

申请日：2008-08-14

申请人： Ravi K. Arimilli ,  Rama K. Govindaraju ,  Peter H. Hochschild ,  Bruce G. Mealey ,  Satya P. Sharma ,  Balaram Sinharoy

发明人： Ravi K. Arimilli ,  Rama K. Govindaraju ,  Peter H. Hochschild ,  Bruce G. Mealey ,  Satya P. Sharma ,  Balaram Sinharoy

IPC分类号： G06F13/00 ,  G06F12/16

CPC分类号： G06F9/3834 ,  G06F9/3004 ,  G06F9/3824

摘要： A system, method, and computer program product for semi-synchronously copying data from a first portion of memory to a second portion of memory are disclosed. The method comprises receiving, in a processor, a call for a semi-synchronous memory copy operation. The semi-synchronous memory copy operation preserves temporal persistence of validity for a virtual source address corresponding to a source location in a memory and a virtual target address corresponding to a target location in the memory by setting a flag bit. The call includes at least the virtual source address, the virtual target address, and an indicator identifying a number of bytes to be copied. The memory copy operation is placed in a queue for execution by a memory controller. The queue is coupled to the memory controller. At least one subsequent instruction is continued to be executed as the subsequent instruction becomes available from an instruction pipeline.

摘要翻译： 公开了一种用于将数据从存储器的第一部分半数同步地复制到存储器的第二部分的系统，方法和计算机程序产品。 该方法包括在处理器中接收对半同步存储器复制操作的呼叫。 半同步存储器复制操作通过设置标志位来保持对应于存储器中的源位置的虚拟源地址和对应于存储器中的目标位置的虚拟目标地址的有效性的时间持续性。 该呼叫至少包括虚拟源地址，虚拟目标地址和标识要复制的字节数的指示符。 存储器复制操作被放置在队列中以由存储器控制器执行。 队列耦合到存储器控制器。 随着随后的指令从指令流水线可用，继续执行至少一个后续指令。

公开(公告)号：US08140801B2

公开(公告)日：2012-03-20

申请号：US12191655

申请日：2008-08-14

申请人： Ravi K. Arimilli ,  Rama K. Govindaraju ,  Peter H. Hochschild ,  Bruce G. Mealey ,  Satya P. Sharma ,  Balaram Sinharoy

发明人： Ravi K. Arimilli ,  Rama K. Govindaraju ,  Peter H. Hochschild ,  Bruce G. Mealey ,  Satya P. Sharma ,  Balaram Sinharoy

IPC分类号： G06F12/00

CPC分类号： G06F9/3834 ,  G06F9/3004 ,  G06F9/3824

摘要： A system, method, and computer program product for semi-synchronously copying data from a first portion of memory to a second portion of memory are disclosed. The method comprises receiving, in a processor, a call for a semi-synchronous memory copy operation. The semi-synchronous memory copy operation preserves temporal persistence of validity for a virtual source address corresponding to a source location in a memory and a virtual target address corresponding to a target location in the memory by setting a flag bit. The call includes at least the virtual source address, the virtual target address, and an indicator identifying a number of bytes to be copied. The memory copy operation is placed in a queue for execution by a memory controller. The queue is coupled to the memory controller. At least one subsequent instruction is continued to be executed as the subsequent instruction becomes available from an instruction pipeline.

摘要翻译： 公开了一种用于将数据从存储器的第一部分半数同步地复制到存储器的第二部分的系统，方法和计算机程序产品。 该方法包括在处理器中接收对半同步存储器复制操作的呼叫。 半同步存储器复制操作通过设置标志位来保持对应于存储器中的源位置的虚拟源地址和对应于存储器中的目标位置的虚拟目标地址的有效性的时间持续性。 该呼叫至少包括虚拟源地址，虚拟目标地址和标识要复制的字节数的指示符。 存储器复制操作被放置在队列中以由存储器控制器执行。 队列耦合到存储器控制器。 随着随后的指令从指令流水线可用，继续执行至少一个后续指令。