摘要:
A transceiver for a LAN is capable of communicating multiple bits per signal element to increase the data throughput of the LAN. The transceiver includes a transmitter which receives a multiple bit digital input value originating at a node of the LAN at which the transceiver is present. The transmitter converts the multiple bit digital input signal into a pulse-like analog signal which is amplitude and phase modulated. A receiver of a transceiver at a receiving node the transmitted analog signal converts its amplitude and phase into a corresponding multiple bit digital output value. A time-domain filter of the receiver creates a primary signal from the received analog signal. To sample the primary signal at its maximum amplitude point, a derivative of the primary signal waveform is used to establish the zero derivative point at which the primary signal attains its maximum amplitude, and to establish a fixed sampling point for subsequent signals. The sampling point is synchronized in phase with the stream of received analog signals. The residual intersymbol interference (ISI) effect of preceding signals on the LAN medium is eliminated prior to converting the primary signal to the digital value. To adjust and compensate for attenuation and amplification created by the LAN medium, the signal values are normalized.
摘要:
A pulse shaping network for the read circuitry of a floppy disc memory system in which encoded digital data is recorded in a double density format. The pulse shaping network processes an uncompensated input read signal in order to substantially eliminate cross talk between the bivalent pulses of the read signal, thereby correcting the peak phase shift and peak amplitude distortion that characterizes intersymbol cross talk. The resulting phase and amplitude corrected read signal can then be accurately decoded in order to retrieve the information contained in the peak phases of the read signal. The pulse shaping network includes a sine pulse-forming filter comprised of a capacitively terminated parallel cascade of series LC sections characterized by respective half-period harmonic transfer functions whose impulse responses are substantially finite time duration sine pulses of a successively odd multiple of half cycles. The input read signal pulses are applied to the sine pulse-forming filter, and a buffer circuit is used to separately tap the responses of the first two LC sections. These responses, which correspond to the convolution of the read signal pulses with the first and third half-period harmonic transfer functions of the filter, are then scaled and applied to a difference amplifier that provides the corrected read signal output of the pulse shaping network. An equalization analysis of the read signal pulses yields the optimum harmonic content, including scaling factors, for the combined network transfer function of the filter so as to substantially eliminate intersymbol cross talk by effectively narrowing in time the pulses of the input read signal. Since the network transfer function is formed of only lower order harmonics, the response of the pulse shaping network is band width-limited so that the signal-to-noise ratio is not seriously degraded.
摘要:
A data processing system applicable for high density magnetic recording and data transmission wherein digital data is translated into multi-level zero average words which occupy a greater number of time slots than the bits of the digital data which they represent, the words having increased power density in the signal spectra thereof which represent the difference between different words. After recording or transmission the signals are detected and decoded in accordance with the amplitude characteristics of samples of the detected signals occurring during time slots which are occupied by samples, the sum of which is equal to zero.
摘要:
An adaptive bit synchronizer is operable to extract digital data and its associated clock from a transmitted digital signal, and includes a tunable matched filter set for modifying the input signal to correct for deviations in offset and gain, which filter set includes data, transition and derivative matched filters. A sampling device samples the output of the data matched filter for making bit decision and for estimating the reliability thereof. A clock-producing device is connected with the matched filter set for producing at least two clocks, use being made of an optimum phase detector for estimating the time error between the proper clock edge and the actual clock edges. A loop filter circuit smooths the estimates of the proper clock time to generate clock signals, and a device responsive to the average square error of the clock signals varies the loop parameters of the loop filter means to minimize average square phase error.
摘要:
A method of developing waveforms having the energy therein concentrated within a limited bandwidth and modems for generating, transmitting, and receiving digital data utilizing such waveforms as carriers. A set of mutually orthogonal basis signals are selected to maximize their energies within the channel, each is binary coded and stored in the modem. A set of optimized coefficients is stored and utilized to weight each basis function in a coding arrangement to define bytes of digital data. The coded and weighted basis functions for each successive byte are summed to form a composite signal and transmitted over the channel as an analog waveform. Stored basis signals at the receiving end are correlated with the received waveform to thereby extract the coefficients which are decoded to reproduce the transmitted bytes. Both coding gain and reduction of intersymbol interference is achieved.
摘要:
A system and method are disclosed for synchronizning the linear PN sequences contained in a received spread spectrum signal, characterized by the provision of a resident PN generator that is responsive to the chip rate clock for producing a replica of the PN sequence with arbitrary phase, a running matrix inverse of the matrix (R) formed by n successive observations of the register of the resident generator, and a matrix vector product device for multiplying the running inverse by a column vector of noisy chips, thereby to obtain a plurality of estimates of the phase vector. These estimates are smoothed and averaged to produce the smoothed phase vector (c.sub.j) that is applied to one input of a dot product device that operates in conjunction with the contents of the shift register of the resident generator to produce the properly phased PN sequence, which sequence is then supplied to despreading means for combining the noisy chips with the properly phased PN sequence. The system may be used for range computation, if desired.
摘要:
A method of transmitting binary data from one station to another via a troposcatter medium, characterized in that the data is converted to parallel form so that the bits produce distinctive pairs of sine and cosine harmonics having different frequencies, which harmonics are summed in two separated channels that are modulated by rf sine and cosine modulating signals that are combined and transmitted to the receiver, together with a test signal that was periodically inserted in the parallel bits. The receiver supplies the signals to banks of matched filters that produce a first set of signal estimates from which the test signal is detected. A matrix system responsive to the test signal produces from the first set of estimates a second set of signal estimates having lower distortion than the first set. When the system is provided with diversity signal transmission at a different rf frequency, the test signal at the receiver is used to provide weighted diversity channel signals that are summed to provide third signal estimates having less distortion than the second set of estimates.
摘要:
A repeatered, multichannel fiber optic communication network includes a plurality of full duplex fiber optic channels and one or more auxiliary channels. In order to supervise and control the operation of the network, for both data transmission and fault/maintenance actions, each terminal station contains a processor-based subsystem capable of network monitoring, first level maintenance action, fault isolation, and remote network control and status reporting. This processor-based subsystem interfaces with each fiber optic channel, with an orderwire communication link, and with external input/output devices and surveillance equipment. Three substantially autonomous processor-based sections which are dedicated to performing specific functions within the overall network operation are employed for carrying out these separate interfacing tasks. Each section of the processor-based subsystem in a terminal station contains its own CPU and associated memory and is programmed to carry out specific functions identified with that section. Each section is interconnected with the other two so that, internally, the subsystem is fully integrated.
摘要:
A wireless data communication system includes a code encoder for transforming pulse code modulated data into a simple code having an alphabet with at least one spare symbol into which a delimiter symbol is introduced, which code is transmitted to a receiver including a matched filter arrangement and a code maximum decision arrangement for decoding the transmitted code signal and for detecting the delimiter symbol.
摘要:
In a communication system containing a scheme for externally synchronizing and scrambling digital data signals, serial digital data signals to be transmitted are subdivided into prescribed numbers or sets between which additional or overhead bits are inserted, the resulting sequence being summed in a modulo-two adder with a multi-bit maximal length PN sequence, so that one of the overhead bits is one of the bits of the maximal length scrambling sequence.A multiplexing operation yields a higher data rate sequence which is then modulo-two added with the output of a scrambler and transmitted.At the receiver station, the incoming scrambled sequence is applied to timing recovery circuitry including a local framing sequence generator. The framing sequence is located and the stages of a separate shift register, which forms part of a descrambler PN sequence generator, are forced to a state which is coincident with the frame marker. This shift register is clocked at the incoming data rate by the recovered clock from a timing recovery circuitry and its output is modulo-two added with the incoming digital data stream, thereby recovering the original multiplexed data.In order to recover the original data, the descrambled sequence is applied to a demultiplexer which effectively deletes every overhead bit and outputs the original data at the original data rate.