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公开(公告)号：US07016826B2
公开(公告)日：2006-03-21
申请号：US09745561
申请日：2000-12-21
CPC分类号： G06F17/5022
摘要： Applications software can be rapidly tested and developed for a multi-processor chip even though the hardware of new processors of the multi-processor chip is not yet available. This can be accomplished by executing software simulations of the new processor designs and corresponding applications software either on a previously designed processor that is hardware on the multi-processor chip or on a workstation development platform. The execution of the previously designed processor is typically much faster than the execution on a simulator running on a personal workstation development platform, and therefore the execution time is quicker. Furthermore, the processor simulation and application software can be configured to take advantage of the platform most appropriate for execution and avoid simulation of portions of the new processors that are not necessary for testing the applications software.
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公开(公告)号：US20090307469A1
公开(公告)日：2009-12-10
申请号：US12477287
申请日：2009-06-03
申请人： Gilbert Wolrich , Matthew J. Adiletta , William R. Wheeler , Debra Bernstein , Donald F. Hooper
发明人： Gilbert Wolrich , Matthew J. Adiletta , William R. Wheeler , Debra Bernstein , Donald F. Hooper
CPC分类号： G06F9/3012 , G06F9/30098 , G06F9/30127 , G06F9/3851
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads or contexts. The processor maintains execution threads. The execution threads access a register set organized into a plurality of relatively addressable windows of registers that are relatively addressable per thread.
摘要翻译： 描述了基于并行硬件的多线程处理器。 处理器包括协调系统功能的通用处理器和支持多个硬件线程或上下文的多个微启动器。 处理器维护执行线程。 执行线程访问组织成每个线程相对可寻址的多个相对可寻址的寄存器窗口的寄存器集。
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公开(公告)号：US06668311B2
公开(公告)日：2003-12-23
申请号：US09919058
申请日：2001-07-30
IPC分类号： G06F1200
CPC分类号： G06F12/023
摘要： An apparatus and method for memory allocation with digital processing systems comprises a first memory bank, a hardware register, and a processing circuit configured to write the contents of the hardware register to a memory address in the first memory bank, and to write the memory address to the hardware register. In an embodiment, a pointer list containing memory pointer values may be maintained in the first memory bank. The first memory bank may contain associated data buffers, and a second memory bank may contain corresponding data buffers such that an associated data buffer and a corresponding data buffer may be located from a single memory pointer value.
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公开(公告)号：US07991983B2
公开(公告)日：2011-08-02
申请号：US12477287
申请日：2009-06-03
CPC分类号： G06F9/3012 , G06F9/30098 , G06F9/30127 , G06F9/3851
摘要： A parallel hardware-based multithreaded processor. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads or contexts. The processor maintains execution threads. The execution threads access a register set organized into a plurality of relatively addressable windows of registers that are relatively addressable per thread.
摘要翻译： 一种基于并行硬件的多线程处理器。 处理器包括协调系统功能的通用处理器和支持多个硬件线程或上下文的多个微启动器。 处理器维护执行线程。 执行线程访问组织成每个线程相对可寻址的多个相对可寻址的寄存器窗口的寄存器集。
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5.发明授权Branch instruction for processor with branching dependent on a specified bit in a register 失效处理器的分支指令，取决于寄存器中指定的位公开(公告)号：US07421572B1
公开(公告)日：2008-09-02
申请号：US10069195
申请日：2000-08-31
申请人： Gilbert Wolrich , Matthew J. Adiletta , William R. Wheeler , Debra Bernstein , Donald F. Hooper
发明人： Gilbert Wolrich , Matthew J. Adiletta , William R. Wheeler , Debra Bernstein , Donald F. Hooper
IPC分类号： G06F9/32
CPC分类号： G06F9/30018 , G06F9/3004 , G06F9/30058 , G06F9/30087 , G06F9/30145 , G06F9/30167 , G06F9/321 , G06F9/3834 , G06F9/3842 , G06F9/3851
摘要： A processor such as a parallel hardware-based multithreaded processor (12) is described. The processor (12) can execute a computer instruction that is a branch instruction that causes an instruction sequence in the processor to branch on any specified bit of a register (80, 78, 76b) being set or cleared and which specifies which bit of the specified register to use as a branch control bit.
摘要翻译： 描述诸如并行硬件的多线程处理器（12）之类的处理器。 处理器（12）可以执行作为分支指令的计算机指令，其使处理器中的指令序列在设置或清零的寄存器（80,78,76b）的任何指定位上分支，并且指定哪个位 指定的寄存器用作分支控制位。
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公开(公告)号：US07546444B1
公开(公告)日：2009-06-09
申请号：US10070091
申请日：2000-08-31
申请人： Gilbert Wolrich , Matthew J. Adiletta , William R. Wheeler , Debra Bernstein , Donald F. Hooper
发明人： Gilbert Wolrich , Matthew J. Adiletta , William R. Wheeler , Debra Bernstein , Donald F. Hooper
CPC分类号： G06F9/3012 , G06F9/30098 , G06F9/30127 , G06F9/3851
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads or contexts (THREAD—3 . . . THREAD—0). The processor maintains execution threads (THREAD—3 . . . THREAD—0) access a register set organized into a plurality of relatively addressable windows of registers that are relatively addressable per thread (THREAD—3 . . . THREAD—0).
摘要翻译： 描述了基于并行硬件的多线程处理器。 该处理器包括协调系统功能的通用处理器和支持多个硬件线程或上下文（THREAD-3，...，THREAD-0）的多个微启动器。 处理器维护执行线程（THREAD-3 ... THREAD-0）访问组织成多个相对可寻址的寄存器窗口的寄存器集合，这些寄存器窗口相对于每个线程可访问（THREAD-3 ... THREAD-0）。
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7.发明授权公开(公告)号：US06823438B2
公开(公告)日：2004-11-23
申请号：US10746876
申请日：2003-12-23
IPC分类号： G06F1200
CPC分类号： G06F12/023
摘要： An apparatus and method for memory allocation with digital processing systems comprises a first memory bank, a hardware register, and a processing circuit configured to write the contents of the hardware register to a memory address in the first memory bank, and to write the memory address to the hardware register. In an embodiment, a pointer list containing memory pointer values may be maintained in the first memory bank. The first memory bank may contain associated data buffers, and a second memory bank may contain corresponding data buffers such that an associated data buffer and a corresponding data buffer may be located from a single memory pointer value.
摘要翻译： 一种用于具有数字处理系统的存储器分配的装置和方法，包括第一存储体，硬件寄存器和配置为将硬件寄存器的内容写入第一存储体中的存储器地址的处理电路，并且将存储器地址 到硬件寄存器。 在一个实施例中，可以在第一存储体中保持包含存储器指针值的指针列表。 第一存储体可以包含相关联的数据缓冲器，并且第二存储体可以包含相应的数据缓冲器，使得可以从单个存储器指针值定位相关联的数据缓冲器和对应的数据缓冲器。
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公开(公告)号：US06671827B2
公开(公告)日：2003-12-30
申请号：US09747018
申请日：2000-12-21
IPC分类号： F11
CPC分类号： G06F11/3636
摘要： A method of debugging code that executes in a multithreaded processor having microengines includes receiving a journal write command and an identification representing a selected one of the microengines from a remote user interface connected to the processor, pausing program execution in the threads executing in the selected microengine, inserting a journal write command at a current program counter in the selected microengine, resuming program execution in the selected microengine, executing a write to a journal routine if program execution in the selected microengine encounters the journal write command and resuming program execution in the microengine.
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9.发明申请公开(公告)号：US20090024804A1
公开(公告)日：2009-01-22
申请号：US12207476
申请日：2008-09-09
IPC分类号： G06F12/10
CPC分类号： G06F13/1642
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.
摘要翻译： 描述了基于并行硬件的多线程处理器。 处理器包括协调系统功能的通用处理器和支持多个硬件线程的多个微启动器。 处理器还包括存储器控制系统，该存储器控制系统具有第一存储器控制器，该第一存储器控制器基于存储器引用是针对偶数存储体还是存储器的奇数存储器来分类存储器引用;以及第二存储器控制器，其基于存储器是否优化存储器引用 引用是读取引用或写入引用。
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公开(公告)号：US07107201B2
公开(公告)日：2006-09-12
申请号：US09941952
申请日：2001-08-29
CPC分类号： G06F17/5022
摘要： Simulating a logic design having combinatorial logic and state logic includes representing the combinatorial logic and the state logic using separate graphic elements, identifying clock domains for the combinatorial logic and the state logic using the separate graphic elements, generating computer code that simulates operation of portions of the logic design, the computer code being generated based on the clock domains, and associating the computer code with graphic elements that correspond to the portions of the logic design.
摘要翻译： 模拟具有组合逻辑和状态逻辑的逻辑设计包括使用分离的图形元素表示组合逻辑和状态逻辑，识别用于组合逻辑的时钟域和使用分离的图形元素的状态逻辑，生成计算机代码，其模拟部分的操作 逻辑设计，基于时钟域产生的计算机代码，以及将计算机代码与对应于逻辑设计的部分的图形元素相关联。
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