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公开(公告)号：US20130135941A1
公开(公告)日：2013-05-30
申请号：US13307884
申请日：2011-11-30
IPC分类号： G11C7/10 , G11C11/402 , G11C7/00
CPC分类号： G11C11/4085 , G11C11/406 , G11C11/4072 , G11C11/4074 , G11C11/4094
摘要： A memory device includes memory cells, each of the memory cells having corresponding bit and word lines connected thereto for accessing the memory cells, a word line circuit coupled with at least one word line, and a bit line circuit coupled with at least one bit line. The memory device further includes at least one control circuit coupled with the bit and word line circuits. The control circuit is operative to cause state information to be stored in the memory cells. At least one switching element selectively connects the memory cells, the bit and word line circuits, and the control circuit to at least one power supply as a function of at least one control signal. The control circuit generates the control signal for disconnecting at least portions of the word line and bit line circuits from the power supply while state information is retained in the memory cells.
摘要翻译： 存储器件包括存储器单元，每个存储器单元具有连接到其上的相应位和字线用于访问存储器单元，与至少一个字线耦合的字线电路和与至少一个位线耦合的位线电路 。 存储器件还包括与位和字线电路耦合的至少一个控制电路。 控制电路用于使状态信息存储在存储单元中。 至少一个开关元件将存储器单元，位和字线电路以及控制电路选择性地连接到作为至少一个控制信号的函数的至少一个电源。 控制电路产生控制信号，用于将字线和位线电路的至少一部分与电源断开，同时将状态信息保留在存储单元中。
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公开(公告)号：US08605489B2
公开(公告)日：2013-12-10
申请号：US13307884
申请日：2011-11-30
CPC分类号： G11C11/4085 , G11C11/406 , G11C11/4072 , G11C11/4074 , G11C11/4094
摘要： A memory device includes memory cells, each of the memory cells having corresponding bit and word lines connected thereto for accessing the memory cells, a word line circuit coupled with at least one word line, and a bit line circuit coupled with at least one bit line. The memory device further includes at least one control circuit coupled with the bit and word line circuits. The control circuit is operative to cause state information to be stored in the memory cells. At least one switching element selectively connects the memory cells, the bit and word line circuits, and the control circuit to at least one power supply as a function of at least one control signal. The control circuit generates the control signal for disconnecting at least portions of the word line and bit line circuits from the power supply while state information is retained in the memory cells.
摘要翻译： 存储器件包括存储器单元，每个存储器单元具有连接到其上的相应位和字线用于访问存储器单元，与至少一个字线耦合的字线电路和与至少一个位线耦合的位线电路 。 存储器件还包括与位和字线电路耦合的至少一个控制电路。 控制电路用于使状态信息存储在存储单元中。 至少一个开关元件将存储器单元，位和字线电路以及控制电路选择性地连接到作为至少一个控制信号的函数的至少一个电源。 控制电路产生控制信号，用于将字线和位线电路的至少一部分与电源断开，同时将状态信息保留在存储单元中。
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公开(公告)号：US07290203B2
公开(公告)日：2007-10-30
申请号：US10977432
申请日：2004-10-29
CPC分类号： G06F12/0893 , G06F11/1064 , G06F2212/1056 , G11C7/1006 , G11C11/406 , G11C11/4096 , G11C2029/0411 , G11C2207/2245 , G11C2211/4062 , Y02D10/13
摘要： Apparatus for passively tracking expired data in a dynamic memory includes an error encoding circuit operative to receive an input data word and to generate an encoded data word which is stored in the dynamic memory. The apparatus further includes a decoding circuit operative to receive an encoded data word from the dynamic memory, to detect at least one or more unidirectional errors in the input data word read from the dynamic memory, and to generate an error signal when at least one error is detected, the error signal indicating that the input data word contains expired data. Control circuitry included in the apparatus is configured for initiating one or more actions in response to the error signal.
摘要翻译： 用于在动态存储器中被动跟踪过期数据的装置包括错误编码电路，其操作以接收输入数据字并产生存储在动态存储器中的编码数据字。 该装置还包括一个解码电路，用于从动态存储器接收编码的数据字，以检测从动态存储器读取的输入数据字中的至少一个或多个单向错误，并且当至少一个错误 检测出指示输入数据字包含过期数据的错误信号。 包括在装置中的控制电路被配置为响应于该误差信号启动一个或多个动作。
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公开(公告)号：US20090019341A1
公开(公告)日：2009-01-15
申请号：US11776810
申请日：2007-07-12
CPC分类号： G06F12/0893 , G06F11/1064 , G06F2212/1056 , G11C7/1006 , G11C11/406 , G11C11/4096 , G11C2029/0411 , G11C2207/2245 , G11C2211/4062 , Y02D10/13
摘要： Apparatus for passively tracking expired data in a dynamic memory includes a time stamp memory configurable for storing information relating to a refresh status of one or more corresponding data entries in the dynamic memory. The apparatus further includes a timer configurable for defining a desired window of time in which a refresh operation of data in the dynamic memory is to occur in order to ensure that the data is valid. Control circuitry is coupled to the time stamp memory and to the timer. The control circuitry is operative to manage the information stored in the time stamp memory relating to the refresh status of the one or more corresponding data entries in the dynamic memory.
摘要翻译： 用于在动态存储器中被动跟踪过期数据的装置包括可配置用于存储与动态存储器中的一个或多个相应数据条目的刷新状态相关的信息的时间戳存储器。 该装置还包括定时器，其可配置用于定义要在其中发生动态存储器中的数据的刷新操作的期望时间窗口，以便确保数据有效。 控制电路耦合到时间戳存储器和定时器。 控制电路用于管理存储在时间戳存储器中的与动态存储器中的一个或多个相应数据条目的刷新状态有关的信息。
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公开(公告)号：US08020073B2
公开(公告)日：2011-09-13
申请号：US11776810
申请日：2007-07-12
IPC分类号： G11C29/00
CPC分类号： G06F12/0893 , G06F11/1064 , G06F2212/1056 , G11C7/1006 , G11C11/406 , G11C11/4096 , G11C2029/0411 , G11C2207/2245 , G11C2211/4062 , Y02D10/13
摘要： Apparatus for passively tracking expired data in a dynamic memory includes a time stamp memory configurable for storing information relating to a refresh status of one or more corresponding data entries in the dynamic memory. The apparatus further includes a timer configurable for defining a desired window of time in which a refresh operation of data in the dynamic memory is to occur in order to ensure that the data is valid. Control circuitry is coupled to the time stamp memory and to the timer. The control circuitry is operative to manage the information stored in the time stamp memory relating to the refresh status of the one or more corresponding data entries in the dynamic memory.
摘要翻译： 用于在动态存储器中被动跟踪过期数据的装置包括可配置用于存储与动态存储器中的一个或多个相应数据条目的刷新状态相关的信息的时间戳存储器。 该装置还包括定时器，其可配置用于定义要在其中发生动态存储器中的数据的刷新操作的期望时间窗口，以便确保数据有效。 控制电路耦合到时间戳存储器和定时器。 控制电路用于管理存储在时间戳存储器中的与动态存储器中的一个或多个相应数据条目的刷新状态有关的信息。
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公开(公告)号：US08860425B2
公开(公告)日：2014-10-14
申请号：US13411068
申请日：2012-03-02
IPC分类号： G01R31/14
CPC分类号： G01R31/3008
摘要： A test circuit for detecting a leakage defect in a circuit under test includes a test stimulus circuit operative to drive an otherwise defect-free, characteristically capacitive node in the circuit under test to a prescribed voltage level, and an observation circuit having at least one threshold and adapted for connection with at least one node in the circuit under test. The observation circuit is operative to detect a voltage level of the node in the circuit under test and to generate an output signal indicative of whether the voltage level of the node is less than the threshold. The voltage level of the node being less than the threshold is indicative of a first type of leakage defect, and the voltage level of the node being greater than the threshold is indicative of a second type of leakage defect.
摘要翻译： 一种用于检测被测电路中的泄漏缺陷的测试电路包括一个测试激励电路，用于将被测电路中的其它无缺陷特征电容性节点驱动到规定的电压电平，以及具有至少一个阈值的观测电路 并且适于与被测电路中的至少一个节点连接。 观察电路可操作以检测被测电路中的节点的电压电平并产生指示节点的电压电平是否小于阈值的输出信号。 节点小于阈值的电压电平表示第一类型的漏电缺陷，并且节点大于阈值的电压电平表示第二类泄漏缺陷。
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公开(公告)号：US08120968B2
公开(公告)日：2012-02-21
申请号：US12704703
申请日：2010-02-12
申请人： William Robert Reohr , John Edward Barth, Jr. , Toshiaki Kirihata , Derek H. Leu , Donald W. Plass
发明人： William Robert Reohr , John Edward Barth, Jr. , Toshiaki Kirihata , Derek H. Leu , Donald W. Plass
IPC分类号： G11C16/06
CPC分类号： G11C8/08 , G11C11/4085
摘要： A word line driver circuit coupled to a memory circuit word line includes pull-up, pull-up clamp, pull-down and pull-down clamp transistors, each having a source, a drain and a gate. For the pull-up transistor, the source is coupled to a first power supply, and the gate to a pull-up control signal. For the pull-up clamp transistor, the source is coupled to the drain of the pull-up transistor, the drain to the word line, and the gate to a pull-up clamp gate signal. For the pull-down transistor, the source is coupled to a second power supply, and the gate to a pull-down control signal. For the pull-down clamp transistor, the source is coupled to the drain of the pull-down transistor, the drain to the word line, and the gate to a pull-down clamp gate signal. The word line is coupled to one or more DRAM cells. Source to drain voltage magnitudes of the pull-up and pull-down transistors are less than a voltage between the first and second power supplies.
摘要翻译： 耦合到存储器电路字线的字线驱动电路包括上拉，上拉钳位，下拉和下拉钳位晶体管，每个具有源极，漏极和栅极。 对于上拉晶体管，源极耦合到第一电源，并将栅极耦合到上拉控制信号。 对于上拉钳位晶体管，源极耦合到上拉晶体管的漏极，到字线的漏极，并将栅极耦合到上拉钳位信号。 对于下拉晶体管，源极耦合到第二电源，并将栅极耦合到下拉控制信号。 对于下拉钳位晶体管，源极耦合到下拉晶体管的漏极，漏极到字线，而栅极耦合到下拉钳位栅极信号。 字线耦合到一个或多个DRAM单元。 源极到漏极上拉和下拉晶体管的电压幅度小于第一和第二电源之间的电压。
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公开(公告)号：US20110199837A1
公开(公告)日：2011-08-18
申请号：US12704703
申请日：2010-02-12
申请人： William Robert Reohr , John Edward Barth, JR. , Toshiaki Kirihata , Derek H. Leu , Donald W. Plass
发明人： William Robert Reohr , John Edward Barth, JR. , Toshiaki Kirihata , Derek H. Leu , Donald W. Plass
CPC分类号： G11C8/08 , G11C11/4085
摘要： A word line driver circuit coupled to a memory circuit word line includes pull-up, pull-up clamp, pull-down and pull-down clamp transistors, each having a source, a drain and a gate. For the pull-up transistor, the source is coupled to a first power supply, and the gate to a pull-up control signal. For the pull-up clamp transistor, the source is coupled to the drain of the pull-up transistor, the drain to the word line, and the gate to a pull-up clamp gate signal. For the pull-down transistor, the source is coupled to a second power supply, and the gate to a pull-down control signal. For the pull-down clamp transistor, the source is coupled to the drain of the pull-down transistor, the drain to the word line, and the gate to a pull-down clamp gate signal. The word line is coupled to one or more DRAM cells. Source to drain voltage magnitudes of the pull-up and pull-down transistors are less than a voltage between the first and second power supplies.
摘要翻译： 耦合到存储器电路字线的字线驱动电路包括上拉，上拉钳位，下拉和下拉钳位晶体管，每个具有源极，漏极和栅极。 对于上拉晶体管，源极耦合到第一电源，并将栅极耦合到上拉控制信号。 对于上拉钳位晶体管，源极耦合到上拉晶体管的漏极，到字线的漏极，并将栅极耦合到上拉钳位信号。 对于下拉晶体管，源极耦合到第二电源，并将栅极耦合到下拉控制信号。 对于下拉钳位晶体管，源极耦合到下拉晶体管的漏极，漏极到字线，而栅极耦合到下拉钳位栅极信号。 字线耦合到一个或多个DRAM单元。 源极到漏极上拉和下拉晶体管的电压幅度小于第一和第二电源之间的电压。
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9.发明授权公开(公告)号：US07945765B2
公开(公告)日：2011-05-17
申请号：US12023495
申请日：2008-01-31
IPC分类号： G06F9/38
CPC分类号： G06F9/3867 , G06F9/383 , G06F9/3869 , G06F9/3873
摘要： An electronic apparatus includes a plurality of stages serially interconnected as a pipeline to perform sequential processings on input operands. A shortening circuit associated with at least one stage of the pipeline recognizes when one or more of input operands for the stage has been predetermined as appropriate for shortening and execute the shortening when appropriate.
摘要翻译： 电子装置包括多个级串联地连接作为流水线，以对输入操作数进行顺序处理。 与流水线的至少一个级相关联的缩短电路识别出当适当的时候，对于阶段的输入操作数中的一个或多个已被预先确定，以便缩短并执行缩短。
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公开(公告)号：US07920434B2
公开(公告)日：2011-04-05
申请号：US12199438
申请日：2008-08-27
IPC分类号： G11C5/00
CPC分类号： G11C11/4091 , G11C11/4097
摘要： Techniques for sensing data states of respective memory cells in a memory array are provided, the memory array including at least a first bit line coupled to at least a subset of the memory cells. In one aspect, a circuit for sensing data states of respective memory cells in the memory array includes at least one sense amplifier coupled to the first bit line. The sense amplifier includes a first transistor operative to selectively inhibit charging of the first bit line in a manner which is independent of a voltage level on a second bit line coupled to the sense amplifier.
摘要翻译： 提供了用于感测存储器阵列中的相应存储器单元的数据状态的技术，所述存储器阵列至少包括耦合到所述存储器单元的至少一个子集的第一位线。 在一个方面，用于感测存储器阵列中各个存储单元的数据状态的电路包括耦合到第一位线的至少一个读出放大器。 感测放大器包括第一晶体管，其操作以选择性地禁止第一位线的充电，其方式与在与读出放大器耦合的第二位线上的电压电平无关。
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