公开(公告)号：US5621245A

公开(公告)日：1997-04-15

申请号：US741526

申请日：1996-10-31

申请人： Willy Agatstein ,  Mostafa Aghazadeh ,  Chia-pin Chiu ,  Amar Ghori ,  James R. Neal ,  Gregory Turturio

发明人： Willy Agatstein ,  Mostafa Aghazadeh ,  Chia-pin Chiu ,  Amar Ghori ,  James R. Neal ,  Gregory Turturio

IPC分类号： G06F1/26 ,  H01L23/498 ,  H01L23/50 ,  H01L25/16 ,  H01L23/34

CPC分类号： H01L25/16 ,  G06F1/26 ,  H01L23/49811 ,  H01L23/50 ,  H01L2924/0002

摘要： A very large scale integrated (VLSI) chip designed to operate at 3.3 volts is modified to be compatible with prior systems having a 5 volt voltage supply. A central processing unit (CPU) is fabricated at a center position on an integrated circuit chip that has an operating voltage of 3.3 volts. The chip is soldered into a pin grid array (PGA) package and a heat sink is attached on the PGA package above the CPU. A 5 volt-to-3.3 volt voltage regulator having a 5 volt input and a 3.3 volt output is placed at an edge of the PGA package. The 3.3 volt output of the voltage regulator is connected to the 3.3 volt operating voltage input of the chip. The VCC 5 V on board pins are connected to the 5 volt input of the voltage regulator and the 3.3 volt output of the voltage regulator is connected to the VCC pins of the chip. VSS ground on board pins are connected in common to both the ground terminal of the voltage regulator and the VSS pads of the chip. High performance capacitors are used to improve the transient response of the on-package voltage regulator. Dual voltage operation of the voltage regulated package is achieved by making the output of the voltage regulator available at the pins of the pin grid array (PGA) package.

摘要翻译： 设计用于3.3伏工作的非常大规模的集成（VLSI）芯片被修改为与具有5伏特电压的现有系统兼容。 中央处理单元（CPU）制造在集成电路芯片的中心位置，该集成电路芯片的工作电压为3.3伏。 该芯片被焊接到引脚格栅阵列（PGA）封装中，散热片连接在CPU上方的PGA封装上。 具有5伏特输入和3.3伏特输出的5伏至3.3伏电压调节器位于PGA封装的边缘。 电压调节器的3.3伏特输出端连接到芯片的3.3伏工作电压输入端。 VCC 5 V板载引脚连接到电压调节器的5 V输入，3.3 V稳压器输出端连接到芯片的VCC引脚。 VSS接地板上的引脚共同连接到电压调节器的接地端子和芯片的VSS焊盘。 高性能电容器用于改善封装内稳压器的瞬态响应。 电压调节封装的双电压工作是通过使引脚格栅阵列（PGA）封装引脚上的电压调节器的输出可用来实现的。

公开(公告)号：US5556811A

公开(公告)日：1996-09-17

申请号：US468972

申请日：1995-06-06

申请人： Willy Agatstein ,  Mostafa Aghazadeh ,  Chia-pin Chiu ,  Amar Ghori ,  James R. Neal ,  Gregory Turturio

发明人： Willy Agatstein ,  Mostafa Aghazadeh ,  Chia-pin Chiu ,  Amar Ghori ,  James R. Neal ,  Gregory Turturio

IPC分类号： G06F1/26 ,  H01L23/498 ,  H01L23/50 ,  H01L25/16 ,  H01L21/60

CPC分类号： H01L25/16 ,  G06F1/26 ,  H01L23/49811 ,  H01L23/50 ,  H01L2924/0002

摘要： A very large scale integrated (VLSI) chip designed to operate at 3.3 volts is modified to be compatible with prior systems having a 5 volt voltage supply. A central processing unit (CPU) is fabricated at a center position on an integrated circuit chip that has an operating voltage of 3.3 volts. The chip is soldered into a pin grid array (PGA) package and a heat sink is attached on the PGA package above the CPU. A 5 volt- to- 3.3 volt voltage regulator having a 5 volt input and a 3.3 volt output is placed at an edge of the PGA package. The 3.3 volt output of the voltage regulator is connected to the 3.3 volt operating voltage input of the chip. The VCC 5V on board pins are connected to the 5 volt input of the voltage regulator and the 3.3 volt output of the voltage regulator is connected to the VCC pins of the chip. VSS ground on board pins are connected in common to both the ground terminal of the voltage regulator and the VSS pads of the chip, High performance capacitors are used to improve the transient response of the on-package voltage regulator. Dual voltage operation of the voltage regulated package is achieved by making the output of the voltage regulator available at the pins of the pin grid array (PGA) package.

摘要翻译： 设计用于3.3伏工作的非常大规模的集成（VLSI）芯片被修改为与具有5伏特电压的现有系统兼容。 中央处理单元（CPU）制造在集成电路芯片的中心位置，该集成电路芯片的工作电压为3.3伏。 该芯片被焊接到引脚格栅阵列（PGA）封装中，散热片连接在CPU上方的PGA封装上。 具有5伏输入和3.3伏输出的5伏至3.3伏稳压器放置在PGA封装的边缘。 电压调节器的3.3伏特输出端连接到芯片的3.3伏工作电压输入端。 VCC 5V板载引脚连接到电压调节器的5伏特输入端，稳压器的3.3伏特输出端连接到芯片的VCC引脚。 VSS接地板上的引脚共同连接到电压调节器的接地端子和芯片的VSS焊盘，高性能电容器用于提高封装电压调节器的瞬态响应。 电压调节封装的双电压工作是通过使引脚格栅阵列（PGA）封装引脚上的电压调节器的输出可用来实现的。

公开(公告)号：US06282714B1

公开(公告)日：2001-08-28

申请号：US08792003

申请日：1997-01-31

申请人： Amar Ghori ,  John White

发明人： Amar Ghori ,  John White

IPC分类号： H04N716

CPC分类号： G09G5/006 ,  G09G2340/02 ,  H04N19/61 ,  H04W88/02

摘要： The present invention provides a digital wireless home computer system. One embodiment of the invention includes a computer with a first digital wireless transceiver, and a home input/output node having a second digital wireless transceiver for communicatively coupling to the first wireless transceiver. This node also has (1) an output device, communicatively coupled to the second wireless transceiver, for presenting an output presentation based on signals received from the computer via the wireless transceivers, and (2) an input device, communicatively coupled to the second wireless transceiver, for receiving input signals from a user interfacing with the home input/output node.

摘要翻译： 本发明提供一种数字无线家庭计算机系统。 本发明的一个实施例包括具有第一数字无线收发器的计算机和具有用于通信地耦合到第一无线收发器的第二数字无线收发器的家庭输入/输出节点。 该节点还具有（1）通信地耦合到第二无线收发器的输出设备，用于经由无线收发器基于从计算机接收的信号呈现输出呈现，以及（2）通信地耦合到第二无线电的输入设备 收发器，用于从与家庭输入/输出节点接口的用户接收输入信号。

公开(公告)号：US5428760A

公开(公告)日：1995-06-27

申请号：US831896

申请日：1992-02-06

申请人： Amar Ghori ,  Herve R. Lambert ,  Steven M. McIntyre

发明人： Amar Ghori ,  Herve R. Lambert ,  Steven M. McIntyre

IPC分类号： G06F12/02 ,  G06F13/16 ,  G06F15/17 ,  G06F12/00

CPC分类号： G06F13/16 ,  G06F12/0284 ,  G06F15/17

摘要： Methods and circuitry for sharing a memory space of a microcontroller with a processor. The memory space corresponds to a random access memory accessible by the microcontroller. The memory space includes random access memory on a same substrate as the microcontroller. The processor is located on a different substrate from the microcontroller. The circuitry includes a slave port for communicating data between the processor and the microcontroller. The slave port receives a logical address and a control signal from the processor. The slave port generates an interrupt signal in response to the control signal. An interrupt server generates memory control signals in response to the interrupt signal. A memory controller reads data from and writes data to the slave port and a memory location associated with the logical address in response to the memory control signals.

摘要翻译： 用于与处理器共享微控制器的存储器空间的方法和电路。 存储器空间对应于由微控制器访问的随机存取存储器。 存储器空间包括与微控制器相同的衬底上的随机存取存储器。 处理器位于与微控制器不同的基板上。 该电路包括用于在处理器和微控制器之间传送数据的从端口。 从端口从处理器接收逻辑地址和控制信号。 从端口响应于控制信号产生中断信号。 中断服务器响应于中断信号产生存储器控制信号。 存储器控制器响应于存储器控制信号，从数据从逻辑端口读取数据并将数据写入逻辑地址。

公开(公告)号：US06754176B1

公开(公告)日：2004-06-22

申请号：US09614395

申请日：2000-07-12

申请人： Rajugopal R. Gubbi ,  Amar Ghori ,  Gregory H. Parks

发明人： Rajugopal R. Gubbi ,  Amar Ghori ,  Gregory H. Parks

IPC分类号： G01R3108

CPC分类号： H04W74/04 ,  H04L12/462

摘要： A scheme for sharing a channel during a contention free period of communications between two or more basic service sets (BSSs) including network components in an overlapping region of a wireless computer network. These network components in the overlapping region may be configured to communicate in contention free periods only. Such bandwidth sharing may then include transmitting within each BSS exclusively during an allocated period of time. Each BSS may include one point coordinator network component and all other network components in the BSS then inform the point coordinator of channel conditions including degradation, and the number of packets received from other BSSs.

摘要翻译： 一种用于在包括无线计算机网络的重叠区域中的网络组件的两个或多个基本服务集（BSS）之间的无争用争用周期期间共享信道的方案。 重叠区域中的这些网络组件可以被配置为仅在无竞争时段内进行通信。 这样的带宽共享然后可以包括在分配的时间段内专门在每个BSS内发送。 每个BSS可以包括一个点协调器网络组件，并且BSS中的所有其他网络组件然后通知点协调器包括衰落以及从其他BSS接收的分组的数量。

公开(公告)号：US06243772B1

公开(公告)日：2001-06-05

申请号：US08792361

申请日：1997-01-31

申请人： Amar Ghori ,  John White

发明人： Amar Ghori ,  John White

IPC分类号： G06F1314

CPC分类号： H04N9/641 ,  H04N5/38 ,  H04N5/4401 ,  H04N21/4622 ,  H04W76/10

摘要： The invention provides a method and apparatus for incorporating an appliance into a computer system. One embodiment of the invention has a computer with a first digital wireless transceiver, and an appliance unit with a second digital wireless transceiver for communicatively coupling to the first wireless transceiver. This appliance unit also has (1) an output device, communicatively coupled to the second wireless transceiver, for presenting an output presentation based on signals received from the computer via the wireless transceivers, and (2) an input device, communicatively coupled to the second wireless transceiver, for receiving input signals from a operator of the appliance unit.

摘要翻译： 本发明提供了一种用于将设备并入到计算机系统中的方法和装置。 本发明的一个实施例具有具有第一数字无线收发器的计算机，以及具有用于通信地耦合到第一无线收发器的第二数字无线收发器的设备单元。 该设备单元还具有（1）通信地耦合到第二无线收发器的输出设备，用于经由无线收发器基于从计算机接收的信号呈现输出呈现，以及（2）输入设备，通信地耦合到第二 无线收发器，用于接收来自设备单元的操作者的输入信号。