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公开(公告)号：US20220028454A1
公开(公告)日：2022-01-27
申请号：US17495778
申请日：2021-10-06
Applicant: Winbond Electronics Corp.
Inventor： Ping-Kun Wang , Ming-Che Lin , Yu-Ting Chen , Chang-Tsung Pai , Shao-Ching Liao , Chi-Ching Liu
Abstract: Provided is a resetting method of a resistive random access memory (RRAM) including the following steps. A first resetting operation and a first verifying operation on the at least one resistive memory cell are performed. Whether to perform a second resetting operation according to a verifying result of the first verifying operation is determined. A second verifying operation is performed after the second resetting operation is determined to be performed and is finished. To determine whether to perform a healing resetting operation according to a verifying result of the second verifying operation, which comprises: performing the healing resetting operation when a verifying current of the second verifying operation is greater than a predetermined current, wherein a resetting voltage of the healing resetting operation is greater than a resetting voltage of the second resetting operation.
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公开(公告)号：US20210057640A1
公开(公告)日：2021-02-25
申请号：US16991055
申请日：2020-08-12
Applicant: Winbond Electronics Corp.
Inventor： Wen-Chia Ou , Chih-Chao Huang , Min-Chih Wei , Yu-Ting Chen , Chi-Ching Liu
Abstract: A method of fabricating a semiconductor device includes the following steps. A plurality of doped regions are formed in a substrate. A first dielectric layer is formed on the substrate. A plurality of first contacts and second contacts are formed in the first dielectric layer to be connected to the plurality of doped regions. A memory element is formed on the first dielectric layer. The memory element is electrically connected to the second contact. A second dielectric layer is formed on the first dielectric layer. The second dielectric layer surrounds the memory element. A conductive line is formed in the second dielectric layer. A top surface of the conductive line is at a same level as a top surface of the memory element, and the conductive line is electrically connected to the plurality of first contacts.
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公开(公告)号：US20210012839A1
公开(公告)日：2021-01-14
申请号：US15930469
申请日：2020-05-13
Applicant: Winbond Electronics Corp.
Inventor： Ping-Kun Wang , Ming-Che Lin , Yu-Ting Chen , Chang-Tsung Pai , Shao-Ching Liao , Chi-Ching Liu
Abstract: Provided is a resistive random access memory (RRAM) including at least one memory cell. The at least one memory cell includes a top electrode, a bottom electrode, a data storage layer, an oxygen gettering layer, a first barrier layer, and an oxygen supplying layer. The data storage layer is disposed between the top electrode and the bottom electrode. The oxygen gettering layer is disposed between the data storage layer and the top electrode. The first barrier layer is disposed between the oxygen gettering layer and the data storage layer. The oxygen supplying layer is disposed between the oxygen gettering layer and the top electrode and/or between the oxygen gettering layer and the first barrier layer.
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公开(公告)号：US11653583B2
公开(公告)日：2023-05-16
申请号：US16922253
申请日：2020-07-07
Applicant: Winbond Electronics Corp.
Inventor： Chang-Tsung Pai , Ming-Che Lin , Chi-Ching Liu , He-Hsuan Chao , Chia-Wen Cheng
IPC: H01L45/00
CPC classification number: H10N70/8833 , H10B63/00 , H10N70/021 , H10N70/841
Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode, a metal oxide layer including a plurality of conductive filament regions formed on the bottom electrode, and a plurality of top electrodes formed on the metal oxide layer, corresponding to the respective conductive filament regions. Each of the conductive filament regions has a bottom portion and a top portion. The width of the bottom portion is greater than that of the top portion. The conductive filament regions include oxygen vacancies, and regions other than the conductive filament regions in the metal oxide layer are nitrogen-containing regions.
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公开(公告)号：US11176996B2
公开(公告)日：2021-11-16
申请号：US15930469
申请日：2020-05-13
Applicant: Winbond Electronics Corp.
Inventor： Ping-Kun Wang , Ming-Che Lin , Yu-Ting Chen , Chang-Tsung Pai , Shao-Ching Liao , Chi-Ching Liu
Abstract: Provided is a resistive random access memory (RRAM) including at least one memory cell. The at least one memory cell includes a top electrode, a bottom electrode, a data storage layer, an oxygen gettering layer, a first barrier layer, and an oxygen supplying layer. The data storage layer is disposed between the top electrode and the bottom electrode. The oxygen gettering layer is disposed between the data storage layer and the top electrode. The first barrier layer is disposed between the oxygen gettering layer and the data storage layer. The oxygen supplying layer is disposed between the oxygen gettering layer and the top electrode and/or between the oxygen gettering layer and the first barrier layer.
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Patent Agency Ranking
公开(公告)号：US11758740B2
公开(公告)日：2023-09-12
申请号：US17224152
申请日：2021-04-07
Applicant: Winbond Electronics Corp.
Inventor： Chang-Tsung Pai , Chiung-Lin Hsu , Yu-Ting Chen , Ming-Che Lin , Chi-Ching Liu
CPC classification number: H10B63/30 , H10N70/011 , H10N70/253 , H10N70/8265 , H10N70/841
Abstract: A three-dimensional semiconductor device includes multiple semiconductor device layers on a substrate, wherein each layer includes a first stacked structure, a first gate dielectric layer, a first semiconductor layer, a first channel layer, a first source region, a first drain region, and a first resistive random access memory cell. The first stacked structure on the substrate includes a first insulating layer and a first gate conductor layer. The first gate dielectric layer surrounds a sidewall of the first stacked structure. The first semiconductor layer surrounds a sidewall of the first gate dielectric layer. The first channel layer is in the first semiconductor layer. The first source region and the first drain region are on both sides of the first channel layer in the first semiconductor layer. The first resistive random access memory cell is on a first sidewall of the first semiconductor layer and connected to the first drain region.
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公开(公告)号：US20210366986A1
公开(公告)日：2021-11-25
申请号：US17224152
申请日：2021-04-07
Applicant: Winbond Electronics Corp.
Inventor： Chang-Tsung Pai , Chiung-Lin Hsu , Yu-Ting Chen , Ming-Che Lin , Chi-Ching Liu
Abstract: A three-dimensional semiconductor device includes multiple semiconductor device layers on a substrate, wherein each layer includes a first stacked structure, a first gate dielectric layer, a first semiconductor layer, a first channel layer, a first source region, a first drain region, and a first resistive random access memory cell. The first stacked structure on the substrate includes a first insulating layer and a first gate conductor layer. The first gate dielectric layer surrounds a sidewall of the first stacked structure. The first semiconductor layer surrounds a sidewall of the first gate dielectric layer. The first channel layer is in the first semiconductor layer. The first source region and the first drain region are on both sides of the first channel layer in the first semiconductor layer. The first resistive random access memory cell is on a first sidewall of the first semiconductor layer and connected to the first drain region.
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公开(公告)号：US10978336B2
公开(公告)日：2021-04-13
申请号：US16704152
申请日：2019-12-05
Applicant: Winbond Electronics Corp.
Inventor： Cheng-Hui Tu , Chi-Ching Liu , Ting-Ying Shen , Yen-De Lee , Ping-Kun Wang
IPC: H01L21/768
Abstract: A method of manufacturing a semiconductor device includes forming a first dielectric layer and a through hole passing through the first dielectric layer over a substrate; forming a plurality of dummy contacts in the through hole; forming a plurality of first dummy wires on the plurality of dummy contacts; filling a second dielectric layer between the plurality of first dummy wires, wherein the second dielectric layer has a first air gap; removing the dummy contacts and the first dummy wires to expose the through hole, thereby forming a first wiring trench over the through hole; and forming a contact and a first wire in the through hole and the first wiring trench.
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公开(公告)号：US12185553B2
公开(公告)日：2024-12-31
申请号：US17715065
申请日：2022-04-07
Applicant: Winbond Electronics Corp.
Inventor： Chi-Ching Liu , Chih-Chao Huang , Ming-Che Lin , Frederick Chen , Han-Huei Hsu
Abstract: Provided is a semiconductor device including: a substrate, a plurality of isolation structures, a plurality of channel layers, and a gate structure. The substrate includes a plurality of fins thereon. The plurality of isolation structures are respectively disposed between the plurality of fins. A top surface of the plurality of isolation structures is higher than a top surface of the plurality of fins to form a plurality of openings. The plurality of channel layers are respectively disposed in the plurality of openings. Each channel layer is in contact with a corresponding fin and extends to cover a lower sidewall of a corresponding isolation structure, thereby forming a U-shaped structure. The gate structure is filled in the plurality of openings and extends to cover the top surface of the plurality of isolation structures.
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公开(公告)号：US12087619B2
公开(公告)日：2024-09-10
申请号：US18087802
申请日：2022-12-22
Applicant: Winbond Electronics Corp.
Inventor： Chi-Ching Liu , Yu-Ting Chen , Chang-Tsung Pai , Shun-Li Lan , Yen-De Lee , Chih-Jung Ni
IPC: H01L21/768 , H10B99/00
CPC classification number: H01L21/76816 , H10B99/00
Abstract: A method for manufacturing a semiconductor device, including the following steps. A plurality of first vias are formed in a first dielectric layer in a memory cell region and a peripheral region. A surface treatment is performed on the plurality of first vias to form a plurality of sacrificial layers. The plurality of sacrificial layers are removed to form a plurality of recesses. A plurality of protective layers are formed in the plurality of recesses. A memory device is formed on the first dielectric layer in the memory cell region. A second dielectric layer is formed on the memory device and on the first dielectric layer. A plurality of second vias is formed in the second dielectric layer in the memory cell region and the peripheral region to electrically connect the memory device in the memory cell region and the first vias in the peripheral region, respectively.
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