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公开(公告)号：US10418113B2
公开(公告)日：2019-09-17
申请号：US16361258
申请日：2019-03-22
Applicant: Winbond Electronics Corp.
Inventor： Naoaki Sudo
Abstract: A NAND flash memory suppresses an influence caused by FG coupling and has high reliability. The flash memory of the invention includes: a memory array formed with a plurality of NAND strings; a row selection unit selecting rows of the memory array; and a bit line selection circuit (200) selecting even-numbered pages or odd-numbered pages of the selected row. The even-numbered pages (BL0, BL1, BL4, BL5) include a plurality of pairs of adjacent bit line pairs, the odd-numbered pages (BL2, BL3, BL6, BL7) include a plurality of pairs of adjacent bit line pairs, and the bit lines of the even-numbered page and the bit lines of the odd-numbered page are arranged alternately.
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公开(公告)号：US10304543B2
公开(公告)日：2019-05-28
申请号：US15666576
申请日：2017-08-02
Applicant: Winbond Electronics Corp.
Inventor： Makoto Senoo , Naoaki Sudo
Abstract: A semiconductor memory device improving a high-temperature data retention is provided. Here, a flash memory includes an erasing element erasing a selected storage cell in a storage cell array. The erasing element further includes an applying element, a verifying element, and a decision element. The applying element applies a monitoring erasing pulse to a monitoring storage cell before starting an erasing operation for selecting the storage cell. The verifying element performs a verification of the monitoring storage cell to which the monitoring erasing pulse is applied. The decision element detennines ISPE conditions based on a verification result of the verifying element. The erasing element erases the storage cell according to the determined ISPE conditions.
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公开(公告)号：US09612753B2
公开(公告)日：2017-04-04
申请号：US14923452
申请日：2015-10-27
Applicant: Winbond Electronics Corp.
Inventor： Naoaki Sudo
CPC classification number: G06F3/061 , G06F3/0638 , G06F3/0679 , G11C7/1006 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3427
Abstract: A semiconductor memory apparatus is provided. The semiconductor memory apparatus does not require additional identification information to perform data scrambling and improves the reliability, where the identification information is used to identify whether it is an erased data or a programmed data. A flash memory of the present disclosure includes a scrambling unit 120 scrambling data between an input/output buffer 110 and a page buffer 160. The scrambling unit 120 includes a writing encoder 200 and a reading decoder 220. When an input data is equal to a predetermined bit string, the writing encoder 200 skips the scrambling of the input data. When a read data of the page buffer 160 is equal to the predetermined bit string, the reading decoder 220 skips the descrambling of the read data.
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公开(公告)号：US20160283113A1
公开(公告)日：2016-09-29
申请号：US14923452
申请日：2015-10-27
Applicant: Winbond Electronics Corp.
Inventor： Naoaki Sudo
IPC: G06F3/06
CPC classification number: G06F3/061 , G06F3/0638 , G06F3/0679 , G11C7/1006 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3427
Abstract: A semiconductor memory apparatus is provided. The semiconductor memory apparatus does not require additional identification information to perform data scrambling and improves the reliability, where the identification information is used to identify whether it is an erased data or a programmed data. A flash memory of the present disclosure includes a scrambling unit 120 scrambling data between an input/output buffer 110 and a page buffer 160. The scrambling unit 120 includes a writing encoder 200 and a reading decoder 220. When an input data is equal to a predetermined bit string, the writing encoder 200 skips the scrambling of the input data. When a read data of the page buffer 160 is equal to the predetermined bit string, the reading decoder 220 skips the descrambling of the read data.
Abstract translation: 提供半导体存储装置。 半导体存储装置不需要额外的识别信息来执行数据加扰并提高可靠性，其中使用识别信息来识别是否是擦除数据或编程数据。 本公开的闪速存储器包括加扰单元120对输入/输出缓冲器110和页缓冲器160之间的数据进行加扰。加扰单元120包括写入编码器200和读取解码器220.当输入数据等于 写入编码器200跳过输入数据的加扰。 当页面缓冲器160的读取数据等于预定位串时，读取解码器220跳过读取数据的解扰。
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公开(公告)号：US20220005511A1
公开(公告)日：2022-01-06
申请号：US17347613
申请日：2021-06-15
Applicant: Winbond Electronics Corp.
Inventor： Naoaki Sudo
IPC: G11C5/14 , G11C11/4074 , G05F1/46
Abstract: A power down detection circuit that may detect a supply voltage decrease more accurately is provided. The power down detection circuit includes a BGR circuit generating a reference voltage VREF, a resistance division circuit generating a first internal voltage VCC_DIV1 and a second internal voltage VCC_DIV2 based on a supply voltage VCC, a first comparator outputting a reset signal PDDRST when detecting VCC_DIV1
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Patent Agency Ranking
公开(公告)号：US20210373644A1
公开(公告)日：2021-12-02
申请号：US16882762
申请日：2020-05-26
Applicant: Winbond Electronics Corp.
Inventor： Naoaki Sudo
IPC: G06F1/3234 , G11C16/30
Abstract: A semiconductor storing apparatus and a flash memory operation method, for shortening a recovery time from a deep power-down (DPD) mode without a dedicated command for the DPD are provided. A flash memory includes: a standard command interface circuit and a DPD controller, operating through an external power voltage; a voltage supply node, for supplying power from the external power voltage via a first current path; a voltage supply node, for supplying power from the external power voltage via a second current path; an internal circuit group, connected to the voltage supply node; and a charge pump circuit, connected to the voltage supply node. When the DPD mode is released, the internal circuit group is enabled after the charge pump circuit is enabled.
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公开(公告)号：US20210257032A1
公开(公告)日：2021-08-19
申请号：US17148591
申请日：2021-01-14
Applicant: Winbond Electronics Corp.
Inventor： Naoaki Sudo
IPC: G11C16/30
Abstract: A semiconductor device capable of automatically transitioning from a standby mode to a deep power down (DPD) mode is provided. The semiconductor device includes: internal circuits capable of operating in response to an input signal from an input/output circuit; and a controller capable of controlling operations of the internal circuits. The internal circuit supporting the DPD mode includes: a measurement part, measuring a time since a time point of the semiconductor device entering the standby mode; a transition time detection part, detecting a case where a measurement time of the measurement part has reached a certain time; and a DPD signal generation part, generating a power down enable signal for further reducing power consumption in the standby mode when a transition time is detected.
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公开(公告)号：US10923209B2
公开(公告)日：2021-02-16
申请号：US15930104
申请日：2020-05-12
Applicant: Winbond Electronics Corp.
Inventor： Naoaki Sudo
Abstract: A semiconductor memory device that can reduce power consumption and precisely perform a power-down operation while a testing operation is underway is provided. A flash memory of the invention has a low-power voltage-detection circuit, a high-precision voltage-detection circuit, and a controller. The low-power voltage-detection circuit detects the supply voltage falling to a constant voltage. The high-precision voltage-detection circuit detects the supply voltage falling to the constant voltage. The controller selects the high-precision voltage-detection circuit when the internal circuit is being tested, and it selects the low-power voltage-detection circuit when the internal circuit is not undergoing a test. The controller responds to the detection result from the low-power voltage-detection circuit or the high-precision voltage-detection circuit by performing a power-down operation.
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公开(公告)号：US10910036B2
公开(公告)日：2021-02-02
申请号：US15930078
申请日：2020-05-12
Applicant: Winbond Electronics Corp.
Inventor： Naoaki Sudo
IPC: G11C11/407 , G11C11/4074 , G11C5/14 , G11C11/4072
Abstract: A semiconductor memory device, which can reduce consuming power and perform a power-off operation correctly, is provided. A flash memory of the invention includes: a low-power-voltage detection circuit detecting that a supply voltage drops to a given voltage; a high-accuracy voltage detection circuit detecting that the supply voltage drops to the given voltage; and a controller selecting the high-accuracy voltage detection circuit when an internal circuit is in an operation state, selecting the low-power-voltage detection circuit when the internal circuit is in a standby state, and performing a power-off operation in response to a detection result of the low-power-voltage detection circuit or the high-accuracy voltage detection circuit.
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公开(公告)号：US20200372959A1
公开(公告)日：2020-11-26
申请号：US16816288
申请日：2020-03-12
Applicant: Winbond Electronics Corp.
Inventor： Naoaki Sudo , Takamichi Kasai , Hiroyuki Kaga
Abstract: A semiconductor storage apparatus capable of realizing continuous read with high speed is provided. A continuous read method of a NAND flash memory includes: a step for holding setting information related to a read time of a memory cell array in continuous read in a register; a step for reading data from the memory cell array in the read time based on the setting information; a step for holding the read data in a latch (L1) and a latch (L2); and a step for outputting the data held synchronously with an external clock signal corresponding to the setting information.
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