公开(公告)号：US20100039852A1

公开(公告)日：2010-02-18

申请号：US12542802

申请日：2009-08-18

申请人： Wing K. Luk ,  Jin Cai

发明人： Wing K. Luk ,  Jin Cai

IPC分类号： G11C11/24 ,  H01L21/8242 ,  G11C7/00

CPC分类号： G11C11/4097 ,  G11C7/18 ,  G11C8/16 ,  G11C11/405 ,  H01L21/28079 ,  H01L21/84 ,  H01L27/10873 ,  H01L29/495

摘要： A dynamic random access memory cell is disclosed that comprises a capacitive storage device and a write access transistor. The write access transistor is operatively coupled to the capacitive storage device and has a gate stack that comprises a high-K dielectric, wherein the high-K dielectric has a dielectric constant greater than a dielectric constant of silicon dioxide. Also disclosed are a memory array using the cells, a computing apparatus using the memory array, a method of storing data, and a method of manufacturing.

摘要翻译： 公开了一种动态随机存取存储器单元，其包括电容存储器件和写入存取晶体管。 写入存取晶体管可操作地耦合到电容存储器件，并且具有包括高K电介质的栅极堆叠，其中高K电介质具有大于二氧化硅介电常数的介电常数。 还公开了使用这些单元的存储器阵列，使用存储器阵列的计算装置，存储数据的方法和制造方法。

公开(公告)号：US20100038695A1

公开(公告)日：2010-02-18

申请号：US12542801

申请日：2009-08-18

申请人： Wing K. Luk ,  Jin Cai

发明人： Wing K. Luk ,  Jin Cai

IPC分类号： H01L27/108

CPC分类号： G11C11/4097 ,  G11C7/18 ,  G11C8/16 ,  G11C11/405 ,  H01L21/28079 ,  H01L21/84 ,  H01L27/10873 ,  H01L29/495

摘要： A dynamic random access memory cell is disclosed that comprises a capacitive storage device and a write access transistor. The write access transistor is operatively coupled to the capacitive storage device and has a gate stack that comprises a high-K dielectric, wherein the high-K dielectric has a dielectric constant greater than a dielectric constant of silicon dioxide. Also disclosed are a memory array using the cells, a computing apparatus using the memory array, a method of storing data, and a method of manufacturing.

摘要翻译： 公开了一种动态随机存取存储器单元，其包括电容存储器件和写入存取晶体管。 写入存取晶体管可操作地耦合到电容存储器件，并且具有包括高K电介质的栅极堆叠，其中高K电介质具有大于二氧化硅介电常数的介电常数。 还公开了使用这些单元的存储器阵列，使用存储器阵列的计算装置，存储数据的方法和制造方法。

公开(公告)号：US08648403B2

公开(公告)日：2014-02-11

申请号：US11408752

申请日：2006-04-21

申请人： Wing K. Luk ,  Jin Cai

发明人： Wing K. Luk ,  Jin Cai

IPC分类号： H01L27/108

CPC分类号： G11C11/4097 ,  G11C7/18 ,  G11C8/16 ,  G11C11/405 ,  H01L21/28079 ,  H01L21/84 ,  H01L27/10873 ,  H01L29/495

摘要： A dynamic random access memory cell is disclosed that comprises a capacitive storage device and a write access transistor. The write access transistor is operatively coupled to the capacitive storage device and has a gate stack that comprises a high-K dielectric, wherein the high-K dielectric has a dielectric constant greater than a dielectric constant of silicon dioxide. Also disclosed are a memory array using the cells, a computing apparatus using the memory array, a method of storing data, and a method of manufacturing.

摘要翻译： 公开了一种动态随机存取存储器单元，其包括电容存储器件和写入存取晶体管。 写入存取晶体管可操作地耦合到电容存储器件，并且具有包括高K电介质的栅极堆叠，其中高K电介质具有大于二氧化硅介电常数的介电常数。 还公开了使用这些单元的存储器阵列，使用存储器阵列的计算装置，存储数据的方法和制造方法。

公开(公告)号：US08445946B2

公开(公告)日：2013-05-21

申请号：US10735061

申请日：2003-12-11

申请人： Wing K. Luk ,  Robert H. Dennard

发明人： Wing K. Luk ,  Robert H. Dennard

IPC分类号： H01L27/108 ,  G11C11/36

CPC分类号： G11C11/405

摘要： A gated diode memory cell is provided, including one or more transistors, such as field effect transistors (“FETs”), and a gated diode in signal communication with the FETs such that the gate of the gated diode is in signal communication with the source of a first FET, wherein the gate of the gated diode forms one terminal of the storage cell and the source of the gated diode forms another terminal of the storage cell, the drain of the first FET being in signal communication with a bitline (“BL”) and the gate of the first FET being in signal communication with a write wordline (“WLw”), and the source of the gated diode being in signal communication with a read wordline (“WLr”).

摘要翻译： 提供了门控二极管存储单元，其包括一个或多个晶体管，例如场效应晶体管（“FET”），以及与FET信号通信的门控二极管，使得门控二极管的栅极与源极信号通信 第一FET的栅极，其中栅极二极管的栅极形成存储单元的一个端子，门控二极管的源极形成存储单元的另一个端子，第一FET的漏极与位线（“BL” “），并且第一FET的栅极与写入字线（”WLw“）进行信号通信，并且门控二极管的源极与读取字线（”WLr“）进行信号通信。

公开(公告)号：US08324667B2

公开(公告)日：2012-12-04

申请号：US10751714

申请日：2004-01-05

申请人： Wing K. Luk ,  Robert H. Dennard

发明人： Wing K. Luk ,  Robert H. Dennard

IPC分类号： H01L29/94

CPC分类号： H03F1/56 ,  G11C7/06 ,  H01L27/0811 ,  H01L29/7391 ,  H03F2200/183

摘要： A circuit comprises a control line and a two terminal semiconductor device having first and second terminals. The first terminal is coupled to a signal line, and the second terminal is coupled to the control line. The two terminal semiconductor device is adapted to have a capacitance when a voltage on the first terminal relative to the second terminal is above a threshold voltage and to have a smaller capacitance when a voltage on the first terminal relative to the second terminal is below the threshold voltage. The control line is coupled to a control signal and the signal line is coupled to a signal and is output of the circuit. A signal is placed on the signal line and voltage on the control line is modified (e.g., raised in the case of n-type devices, or lowered for a p-type devices). When the signal falls below the threshold voltage, the two terminal semiconductor device acts as a very small capacitor and the output of the circuit will be a small value. When the signal is above the threshold voltage, the two terminal semiconductor device acts as a large capacitor and the output of the circuit will be influenced by both the value of the signal and the value of the modified voltage on the control line and therefore the signal will be amplified.

公开(公告)号：US07983186B2

公开(公告)日：2011-07-19

申请号：US12558055

申请日：2009-09-11

申请人： John E. Breeding ,  Michael E. Casey ,  Jimmy Everman ,  William F. Jones ,  Wing K. Luk ,  Johnny H. Reed

发明人： John E. Breeding ,  Michael E. Casey ,  Jimmy Everman ,  William F. Jones ,  Wing K. Luk ,  Johnny H. Reed

IPC分类号： H04L12/26

CPC分类号： G01T1/00 ,  H04L67/12 ,  H04L69/40

摘要： A system identifies when received packets are lost at a node in a multi-node processing chain. The system processing chain may include a gantry interface module for receiving coincident event data from a PET (Positron Emission Tomography) detector array, a DMA (direct memory access) rebinner card, and a transmission line coupled between the gantry interface module and the DMA card. FPGA and FIFO elements in each processing portion receive packets that may be lost if there is insufficient FIFO capacity. Lost packets are marked, discarded, and counted. At specified intervals, set in accordance with a threshold number of packets received a lost tally data packet is generated that includes count information for lost packets. The lost tally data packet is forwarded downstream when sufficient storage capacity exists.

摘要翻译： 系统识别在多节点处理链中的节点处收到的数据包丢失的情况。 系统处理链可以包括用于从PET（正电子发射断层扫描）检测器阵列，DMA（直接存储器访问）重新接收器卡和耦合在台架接口模块和DMA卡之间的传输线接收重合事件数据的龙门架接口模块 。 每个处理部分的FPGA和FIFO元素接收到如果FIFO容量不足可能会丢失的数据包。 丢失的数据包被标记，丢弃和计数。 按指定间隔设置，根据接收到的丢包数据包的阈值数量，生成包括丢失数据包的计数信息。 当存在足够的存储容量时，丢失的计数数据分组被转发到下游。

公开(公告)号：US07466617B2

公开(公告)日：2008-12-16

申请号：US11623434

申请日：2007-01-16

申请人： Wing K. Luk ,  Brian L. Ji

发明人： Wing K. Luk ,  Brian L. Ji

IPC分类号： G11C11/34

CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C8/16 ,  G11C11/403 ,  G11C11/405 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2211/4065

摘要： A dynamic random access memory circuit has at least one write bit line, at least one read bit line, a capacitive storage device, a write access device operatively coupled to the capacitive storage device and the at least one write bit line, a sense amplifier operatively coupled to the at least one read bit line and configured to generate an output signal, and a refresh bypass device operatively associated with the sense amplifier and the at least one write bit line so as to selectively pass the output signal to the at least one write bit line.

摘要翻译： 动态随机存取存储器电路具有至少一个写位线，至少一个读位线，电容存储器件，可操作地耦合到电容存储器件和至少一个写位线的写访问器件， 耦合到所述至少一个读取位线并被配置为产生输出信号;以及刷新旁路装置，其可操作地与所述读出放大器和所述至少一个写入位线相关联，以便选择性地将所述输出信号传递到所述至少一个写入 位线。

公开(公告)号：US07116594B2

公开(公告)日：2006-10-03

申请号：US10933706

申请日：2004-09-03

申请人： Wing K. Luk ,  Leland Chang ,  Robert H. Dennard ,  Robert Montoye

发明人： Wing K. Luk ,  Leland Chang ,  Robert H. Dennard ,  Robert Montoye

IPC分类号： G11C7/00 ,  G11C7/02 ,  G01R19/00 ,  H03F3/60

CPC分类号： G11C7/065 ,  G11C7/06 ,  H03F1/56 ,  H03F3/10 ,  H03F3/347 ,  H03F2200/183

摘要： A sense amplifier circuit comprises (1) an isolation device comprising a control terminal and first and second terminals, the first terminal of the isolation device coupled to a signal line, (2) a gated diode comprising first and second terminals, the first terminal of the gated diode coupled to the second terminal of the isolation device, and the second terminal of the gated diode coupled to a set line; and (3) control circuitry coupled to the control terminal of the isolation device and adapted to control voltage on the control terminal of the isolation device in order to enable and disable the isolation device. A latch circuit further comprises a precharge device comprising a control terminal and first and second terminals, the first terminal of the precharge device coupled to a power supply voltage, and the second terminal of the precharge device coupled to the first terminal of the isolation device.

摘要翻译： 读出放大器电路包括（1）隔离装置，其包括控制端子和第一和第二端子，隔离装置的第一端子耦合到信号线，（2）门控二极管，包括第一和第二端子，第一端子 所述门控二极管耦合到隔离装置的第二端子，并且门控二极管的第二端子耦合到设定线路; 和（3）耦合到隔离装置的控制端子并且适于控制隔离装置的控制端子上的电压的控制电路，以便启用和禁用隔离装置。 闩锁电路还包括预充电装置，其包括控制端子和第一和第二端子，预充电装置的第一端子耦合到电源电压，并且预充电装置的第二端子耦合到隔离装置的第一端子。

公开(公告)号：US06999370B2

公开(公告)日：2006-02-14

申请号：US10635331

申请日：2003-08-06

申请人： Wing K. Luk ,  Robert H. Dennard ,  Stephen V. Kosonocky

发明人： Wing K. Luk ,  Robert H. Dennard ,  Stephen V. Kosonocky

IPC分类号： G11C7/00

CPC分类号： G11C5/063 ,  G11C11/406 ,  G11C11/4074 ,  G11C2207/104

摘要： An integrated circuit, such as a memory macro, includes multiple power rails supporting first and second voltage differentials, with the second voltage differential being smaller than the first voltage differential. Signal lines in the integrated circuit are driven with the small voltage swing, which is generated by small swing circuits. The integrated circuit further includes regeneration circuits, which are receiving small voltage swing inputs and are outputting first, or full voltage swings. The application of the small voltage swing to the signal lines saves power in the integrated circuit. A wide bandwidth, full-wordline I/O, memory integrated circuit has simultaneously operable connection paths between essentially all the memory cells that are attached to the same wordline and the corresponding I/O terminals, and it has a single ended data-line structure.

摘要翻译： 诸如存储器宏的集成电路包括支持第一和第二电压差的多个电源轨，第二电压差小于第一电压差。 集成电路中的信号线由小的摆动电路产生的小电压摆动驱动。 集成电路还包括正在接收小电压摆幅输入并且正在输出第一或全电压摆幅的再生电路。 将小电压摆幅应用于信号线节省了集成电路中的功率。 宽带宽全字I / O存储器集成电路在连接到同一字线和对应的I / O端子的基本上所有的存储器单元之间具有同时可操作的连接路径，并且具有单端数据线结构 。

公开(公告)号：US08675403B2

公开(公告)日：2014-03-18

申请号：US13571094

申请日：2012-08-09

申请人： Wing K. Luk ,  Robert H. Dennard

发明人： Wing K. Luk ,  Robert H. Dennard

IPC分类号： G11C11/14

CPC分类号： G11C11/36 ,  G11C11/404

摘要： A gated diode memory cell is provided, including one or more transistors, such as field effect transistors (“FETs”), and a gated diode in signal communication with the FETs such that the gate of the gated diode is in signal communication with the source of a first FET, wherein the gate of the gated diode forms one terminal of the storage cell and the source of the gated diode forms another terminal of the storage cell, the drain of the first FET being in signal communication with a bitline (“BL”) and the gate of the first FET being in signal communication with a write wordline (“WLw”), and the source of the gated diode being in signal communication with a read wordline (“WLr”).

摘要翻译： 提供了门控二极管存储单元，其包括一个或多个晶体管，例如场效应晶体管（“FET”），以及与FET信号通信的门控二极管，使得门控二极管的栅极与源极信号通信 第一FET的栅极，其中栅极二极管的栅极形成存储单元的一个端子，门控二极管的源极形成存储单元的另一个端子，第一FET的漏极与位线（“BL” “），并且第一FET的栅极与写入字线（”WLw“）进行信号通信，并且门控二极管的源极与读取字线（”WLr“）进行信号通信。