公开(公告)号：US20060255850A1

公开(公告)日：2006-11-16

申请号：US11491701

申请日：2006-07-24

申请人： Wing Luk ,  Leland Chang ,  Robert Dennard ,  Robert Montoye

发明人： Wing Luk ,  Leland Chang ,  Robert Dennard ,  Robert Montoye

IPC分类号： H03K3/356

CPC分类号： G11C7/065 ,  G11C7/06 ,  H03F1/56 ,  H03F3/10 ,  H03F3/347 ,  H03F2200/183

摘要： A sense amplifier circuit comprises (1) an isolation device comprising a control terminal and first and second terminals, the first terminal of the isolation device coupled to a signal line, (2) a gated diode comprising first and second terminals, the first terminal of the gated diode coupled to the second terminal of the isolation device, and the second terminal of the gated diode coupled to a set line; and (3) control circuitry coupled to the control terminal of the isolation device and adapted to control voltage on the control terminal of the isolation device in order to enable and disable the isolation device. A latch circuit further comprises a precharge device comprising a control terminal and first and second terminals, the first terminal of the precharge device coupled to a power supply voltage, and the second terminal of the precharge device coupled to the first terminal of the isolation device.

摘要翻译： 读出放大器电路包括（1）隔离装置，其包括控制端子和第一和第二端子，隔离装置的第一端子耦合到信号线，（2）门控二极管，包括第一和第二端子，第一端子 所述门控二极管耦合到隔离装置的第二端子，并且门控二极管的第二端子耦合到设定线路; 和（3）耦合到隔离装置的控制端子并且适于控制隔离装置的控制端子上的电压的控制电路，以便启用和禁用隔离装置。 闩锁电路还包括预充电装置，其包括控制端子和第一和第二端子，预充电装置的第一端子耦合到电源电压，并且预充电装置的第二端子耦合到隔离装置的第一端子。

公开(公告)号：US20060050581A1

公开(公告)日：2006-03-09

申请号：US10933706

申请日：2004-09-03

申请人： Wing Luk ,  Leland Chang ,  Robert Dennard ,  Robert Montoye

发明人： Wing Luk ,  Leland Chang ,  Robert Dennard ,  Robert Montoye

IPC分类号： G11C7/00

CPC分类号： G11C7/065 ,  G11C7/06 ,  H03F1/56 ,  H03F3/10 ,  H03F3/347 ,  H03F2200/183

摘要： A sense amplifier circuit comprises (1) an isolation device comprising a control terminal and first and second terminals, the first terminal of the isolation device coupled to a signal line, (2) a gated diode comprising first and second terminals, the first terminal of the gated diode coupled to the second terminal of the isolation device, and the second terminal of the gated diode coupled to a set line; and (3) control circuitry coupled to the control terminal of the isolation device and adapted to control voltage on the control terminal of the isolation device in order to enable and disable the isolation device. A latch circuit further comprises a precharge device comprising a control terminal and first and second terminals, the first terminal of the precharge device coupled to a power supply voltage, and the second terminal of the precharge device coupled to the first terminal of the isolation device.

公开(公告)号：US07116594B2

公开(公告)日：2006-10-03

申请号：US10933706

申请日：2004-09-03

申请人： Wing K. Luk ,  Leland Chang ,  Robert H. Dennard ,  Robert Montoye

发明人： Wing K. Luk ,  Leland Chang ,  Robert H. Dennard ,  Robert Montoye

IPC分类号： G11C7/00 ,  G11C7/02 ,  G01R19/00 ,  H03F3/60

CPC分类号： G11C7/065 ,  G11C7/06 ,  H03F1/56 ,  H03F3/10 ,  H03F3/347 ,  H03F2200/183

摘要： A sense amplifier circuit comprises (1) an isolation device comprising a control terminal and first and second terminals, the first terminal of the isolation device coupled to a signal line, (2) a gated diode comprising first and second terminals, the first terminal of the gated diode coupled to the second terminal of the isolation device, and the second terminal of the gated diode coupled to a set line; and (3) control circuitry coupled to the control terminal of the isolation device and adapted to control voltage on the control terminal of the isolation device in order to enable and disable the isolation device. A latch circuit further comprises a precharge device comprising a control terminal and first and second terminals, the first terminal of the precharge device coupled to a power supply voltage, and the second terminal of the precharge device coupled to the first terminal of the isolation device.

摘要翻译： 读出放大器电路包括（1）隔离装置，其包括控制端子和第一和第二端子，隔离装置的第一端子耦合到信号线，（2）门控二极管，包括第一和第二端子，第一端子 所述门控二极管耦合到隔离装置的第二端子，并且门控二极管的第二端子耦合到设定线路; 和（3）耦合到隔离装置的控制端子并且适于控制隔离装置的控制端子上的电压的控制电路，以便启用和禁用隔离装置。 闩锁电路还包括预充电装置，其包括控制端子和第一和第二端子，预充电装置的第一端子耦合到电源电压，并且预充电装置的第二端子耦合到隔离装置的第一端子。

公开(公告)号：US07242629B2

公开(公告)日：2007-07-10

申请号：US11491701

申请日：2006-07-24

申请人： Wing K. Luk ,  Leland Chang ,  Robert H. Dennard ,  Robert Montoye

发明人： Wing K. Luk ,  Leland Chang ,  Robert H. Dennard ,  Robert Montoye

IPC分类号： G11C7/00 ,  G11C7/02 ,  G01R19/00 ,  H03F3/60

CPC分类号： G11C7/065 ,  G11C7/06 ,  H03F1/56 ,  H03F3/10 ,  H03F3/347 ,  H03F2200/183

摘要： A sense amplifier circuit comprises (1) an isolation device comprising a control terminal and first and second terminals, the first terminal of the isolation device coupled to a signal line, (2) a gated diode comprising first and second terminals, the first terminal of the gated diode coupled to the second terminal of the isolation device, and the second terminal of the gated diode coupled to a set line; and (3) control circuitry coupled to the control terminal of the isolation device and adapted to control voltage on the control terminal of the isolation device in order to enable and disable the isolation device. A latch circuit further comprises a precharge device comprising a control terminal and first and second terminals, the first terminal of the precharge device coupled to a power supply voltage, and the second terminal of the precharge device coupled to the first terminal of the isolation device.

摘要翻译： 读出放大器电路包括（1）隔离装置，其包括控制端子和第一和第二端子，隔离装置的第一端子耦合到信号线，（2）门控二极管，包括第一和第二端子，第一端子 所述门控二极管耦合到隔离装置的第二端子，并且门控二极管的第二端子耦合到设定线路; 和（3）耦合到隔离装置的控制端子并且适于控制隔离装置的控制端子上的电压的控制电路，以便启用和禁用隔离装置。 闩锁电路还包括预充电装置，其包括控制端子和第一和第二端子，预充电装置的第一端子耦合到电源电压，并且预充电装置的第二端子耦合到隔离装置的第一端子。

公开(公告)号：US20050071717A1

公开(公告)日：2005-03-31

申请号：US10670832

申请日：2003-09-25

申请人： Wendy Belluomini ,  Andrew Martin ,  Chandler McDowell ,  Robert Montoye

发明人： Wendy Belluomini ,  Andrew Martin ,  Chandler McDowell ,  Robert Montoye

IPC分类号： G01R31/3185 ,  G11C29/00 ,  G01R31/28

CPC分类号： G01R31/318572 ,  G11C29/003

摘要： A method and system for manipulating data in a state holding elements array. Process data is moved through the state holding elements array by a process controller. A separate scan controller scans data out of the state holding elements array by scanning data out of a group of cascaded latches where there are insufficient extra state holding elements in the group to enable normal scan. A multiplicity of local scan clocks are utilized to shift selected amounts of data only when a next state holding element in the group has been made available by clearing the contents of that next state holding element. In this way, any given latch, for the purpose of scan, is not a dedicated master or slave latch, but can act as either. This invention also addresses a circuit for the creation of the multiplicity of local clocks from a conventional LSSD clock source.

摘要翻译： 用于在保持元素数组的状态下操作数据的方法和系统。 过程控制器将过程数据移动通过状态保持元素数组。 单独的扫描控制器通过从组中不充足的额外状态保持元件的一组级联锁存器扫描数据来扫描状态保持元件阵列中的数据，以启用正常扫描。 仅当通过清除该下一状态保持元件的内容已经使该组中的下一状态保持元件可用时，才使用多个本地扫描时钟来移位所选择的数据量。 以这种方式，为了扫描的目的，任何给定的锁存器不是专用的主器件或从器件锁存器，而是可以作为任一个。 本发明还涉及用于从常规LSSD时钟源产生多个本地时钟的电路。

公开(公告)号：US20060290385A1

公开(公告)日：2006-12-28

申请号：US11168718

申请日：2005-06-28

申请人： Wendy Belluomini ,  Robert Montoye ,  Aniket Saha

发明人： Wendy Belluomini ,  Robert Montoye ,  Aniket Saha

IPC分类号： H03K19/096

CPC分类号： H03K19/0963

摘要： A dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock controlled provides increased noise immunity in dynamic digital circuits. By clocking the pre-charge element with a signal having a reduced swing in the voltage direction that turns off the pre-charge element, the pre-charge element provides a small current that prevents the dynamic summing node of a gate from erroneously evaluating due to noise, and eliminates the need for a keeper device. Providing the reduced-swing asymmetric clock as a separate signal prevents performance degradation in the rest of the circuit. Specifically, the foot devices in the dynamic portion of the circuit are controlled with the full swing clock so that evaluation is not compromised by noise or slowed. Foot and pull-up devices in any static portion of the circuit are also controlled with the full-swing clock so that switching speed and leakage immunity are not affected.

摘要翻译： 具有由电压非对称时钟控制的预充电元件的动态逻辑电路在动态数字电路中提供了增强的抗噪声能力。 通过对具有减小预充电元件的电压方向上的摆幅减小的信号对预充电元件进行计时，预充电元件提供小电流，防止栅极的动态求和节点由于 噪音，并且消除了对保持装置的需要。 将降频摆动非对称时钟提供为单独的信号可防止电路其余部分的性能下降。 具体地说，利用全摆动时钟来控制电路的动态部分中的脚部装置，使得评估不会受到噪声的影响或减慢。 电路的任何静态部分中的脚踏和上拉器件也可以通过全频时钟控制，从而不影响开关速度和漏电抗扰度。

公开(公告)号：US20060190704A1

公开(公告)日：2006-08-24

申请号：US11065602

申请日：2005-02-24

申请人： Peter Capek ,  Robert Montoye

发明人： Peter Capek ,  Robert Montoye

IPC分类号： G06F9/30

CPC分类号： G06F9/3016

摘要： An apparatus for increasing addressability of registers within a processor is disclosed. The apparatus includes a set of apparent registers and a set of real registers. The total number of real registers is substantially higher than the total number of apparent registers such that only a subset of the real registers is referenced by all of the apparent registers at any given time. Any one of the real registers can be designated by an instruction via one of the apparent registers. Any one of the actual registers can also be directly designated by an instruction.

摘要翻译： 公开了一种用于增加处理器内的寄存器的寻址能力的装置。 该装置包括一组视在寄存器和一组实际寄存器。 实际寄存器的总数明显高于表观寄存器的总数，使得在任何给定时间只有所有的表观寄存器都只引用实际寄存器的一个子集。 任何一个实际寄存器都可以通过一个指令通过一个表观寄存器来指定。 任何一个实际寄存器也可以由指令直接指定。

公开(公告)号：US20050139647A1

公开(公告)日：2005-06-30

申请号：US10745730

申请日：2003-12-24

申请人： Ramyanshu Datta ,  Robert Montoye

发明人： Ramyanshu Datta ,  Robert Montoye

IPC分类号： G06F1/00 ,  G06F7/76

CPC分类号： G06F7/76

摘要： A method and apparatus for performing bit-aligned permute are disclosed. A select register, a pair of data registers and a target register are provided. The entries of the select register is preloaded with a set of bit indices. Each of the bit indices points to a desired bit location within the data registers. The byte information stored in the data registers are then copied to the target register according to the bit indices within the select register.

摘要翻译： 公开了一种用于执行位对齐排列的方法和装置。 提供一个选择寄存器，一对数据寄存器和一个目标寄存器。 选择寄存器的条目预先加载一组位索引。 每个比特索引指向数据寄存器内的所需比特位置。 存储在数据寄存器中的字节信息然后根据选择寄存器中的位索引被复制到目标寄存器。

公开(公告)号：US20070226466A1

公开(公告)日：2007-09-27

申请号：US11366884

申请日：2006-03-02

申请人： Peter Capek ,  Jeffrey Derby ,  Robert Montoye

发明人： Peter Capek ,  Jeffrey Derby ,  Robert Montoye

IPC分类号： G06F9/30

CPC分类号： G06F9/3012 ,  G06F9/3004 ,  G06F9/30098 ,  G06F9/3013 ,  G06F9/30138 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/35 ,  G06F9/384

摘要： A facility is provided for managing register maps for map-based indirect register file access within a processor. The management facility includes a register mapping including a set of maps, each map of the set of maps having a plurality of map registers. A set of actual registers is indirectly accessed by the processor via map entries of the set of maps. The number of actual registers in the set of actual registers is greater than the number of map entries in the set of maps, and the map entries of the set of maps reference only a subset of the set of actual registers at any given time. The facility includes managing updates to multiple entries of the set of maps of the register mapping by updating multiple map entries of at least one map of the set of maps responsive to executing a single update instruction.

摘要翻译： 提供了一种用于管理处理器内基于地图的间接寄存器文件访问的寄存器映射的设施。 管理设施包括包括一组映射的寄存器映射，该映射集合的每个映射具有多个映射寄存器。 一组实际寄存器由处理器通过地图集的映射条目间接访问。 实际寄存器组中实际寄存器的数量大于映射集中映射条目的数量，映射集合的映射条目仅引用任何给定时间的实际寄存器集合的子集。 该设施包括通过基于执行单个更新指令来更新该组映射的至少一个映射的多个映射条目来管理对该映射映射集合的多个条目的更新。

公开(公告)号：US20070216457A1

公开(公告)日：2007-09-20

申请号：US11377507

申请日：2006-03-16

申请人： Kanak Agarwal ,  Robert Montoye

发明人： Kanak Agarwal ,  Robert Montoye

IPC分类号： H03K3/017

CPC分类号： H03K5/1565

摘要： Methods and arrangements to adjust a duty cycle of a clock signal are disclosed. Embodiments may include a duty cycle controller to adjust the duty cycle of the clock signal based upon a delay signal and an input clock signal. A duty cycle detector may determine signals with frequencies based upon the duty cycle of the output signal and a correction module may compare the frequencies of the detector signals to generate the delay signal. In some embodiments, once the duty cycle of the output clock signal reaches the desired duty cycle such as fifty percent, the correction module may be turned off.

摘要翻译： 公开了调整时钟信号占空比的方法和装置。 实施例可以包括占空比控制器，用于基于延迟信号和输入时钟信号来调整时钟信号的占空比。 占空比检测器可以基于输出信号的占空比来确定具有频率的信号，并且校正模块可以比较检测器信号的频率以产生延迟信号。 在一些实施例中，一旦输出时钟信号的占空比达到期望的占空比（例如百分之五十），则校正模块可以被关断。