公开(公告)号：US08716825B2

公开(公告)日：2014-05-06

申请号：US13166091

申请日：2011-06-22

申请人： Wing-Chor Chan ,  Chung-Yu Hung ,  Chien-Wen Chu

发明人： Wing-Chor Chan ,  Chung-Yu Hung ,  Chien-Wen Chu

IPC分类号： H01L29/66

CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0649 ,  H01L29/402

摘要： A semiconductor structure and a manufacturing method for the same are provided. The semiconductor structure includes a well region, a dielectric structure, a first doped layer, a second doped layer and a first doped region. The dielectric structure is on the well region. The dielectric structure has a first dielectric sidewall and a second dielectric sidewall opposite to each other. The dielectric structure includes a first dielectric portion and a second dielectric portion, between the first dielectric sidewall and the second dielectric sidewall. The first doped layer is on the well region between the first dielectric portion and the second dielectric portion. The second doped layer is on the first doped layer. The first doped region is in the well region on the first dielectric sidewall.

摘要翻译： 提供了一种半导体结构及其制造方法。 半导体结构包括阱区，电介质结构，第一掺杂层，第二掺杂层和第一掺杂区。 电介质结构在阱区上。 电介质结构具有彼此相对的第一电介质侧壁和第二电介质侧壁。 电介质结构包括在第一电介质侧壁和第二电介质侧壁之间的第一电介质部分和第二电介质部分。 第一掺杂层位于第一电介质部分和第二电介质部分之间的阱区上。 第二掺杂层在第一掺杂层上。 第一掺杂区位于第一电介质侧壁上的阱区中。

公开(公告)号：US20120326261A1

公开(公告)日：2012-12-27

申请号：US13166091

申请日：2011-06-22

申请人： Wing-Chor Chan ,  Chung-Yu Hung ,  Chien-Wen Chu

发明人： Wing-Chor Chan ,  Chung-Yu Hung ,  Chien-Wen Chu

IPC分类号： H01L29/872 ,  H01L21/329

CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0649 ,  H01L29/402

摘要： A semiconductor structure and a manufacturing method for the same are provided. The semiconductor structure includes a well region, a dielectric structure, a first doped layer, a second doped layer and a first doped region. The dielectric structure is on the well region. The dielectric structure has a first dielectric sidewall and a second dielectric sidewall opposite to each other. The dielectric structure includes a first dielectric portion and a second dielectric portion, between the first dielectric sidewall and the second dielectric sidewall. The first doped layer is on the well region between the first dielectric portion and the second dielectric portion. The second doped layer is on the first doped layer. The first doped region is in the well region on the first dielectric sidewall.

摘要翻译： 提供了一种半导体结构及其制造方法。 半导体结构包括阱区，电介质结构，第一掺杂层，第二掺杂层和第一掺杂区。 电介质结构在阱区上。 电介质结构具有彼此相对的第一电介质侧壁和第二电介质侧壁。 电介质结构包括在第一电介质侧壁和第二电介质侧壁之间的第一电介质部分和第二电介质部分。 第一掺杂层位于第一电介质部分和第二电介质部分之间的阱区上。 第二掺杂层在第一掺杂层上。 第一掺杂区位于第一电介质侧壁上的阱区中。

公开(公告)号：US08482066B2

公开(公告)日：2013-07-09

申请号：US13225189

申请日：2011-09-02

申请人： Chien-Wen Chu ,  Wing-Chor Chan ,  Shyi-Yuan Wu

发明人： Chien-Wen Chu ,  Wing-Chor Chan ,  Shyi-Yuan Wu

IPC分类号： H01L31/119

CPC分类号： H01L29/7816 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1087 ,  H01L29/42368 ,  H01L29/7393 ,  H01L29/7394 ,  H01L29/7824

摘要： A semiconductor device and a manufacturing method for the same are provided. The semiconductor device comprises a first doped region, a second doped region, a dielectric structure and a gate structure. The first doped region has a first type conductivity. The second doped region has a second type conductivity opposite to the first type conductivity and is adjacent to the first doped region. The dielectric structure comprises a first dielectric portion and a second dielectric portion separated from each other. The dielectric structure is formed on the first doped region. The gate structure is on a part of the first doped region or second doped region adjacent to the first dielectric portion.

摘要翻译： 提供了一种半导体器件及其制造方法。 半导体器件包括第一掺杂区，第二掺杂区，电介质结构和栅极结构。 第一掺杂区域具有第一类型的导电性。 第二掺杂区域具有与第一类型导电性相反的第二类型导电性，并且与第一掺杂区域相邻。 电介质结构包括彼此分离的第一电介质部分和第二电介质部分。 电介质结构形成在第一掺杂区域上。 栅极结构位于与第一电介质部分相邻的第一掺杂区域或第二掺杂区域的一部分上。

公开(公告)号：US09029952B2

公开(公告)日：2015-05-12

申请号：US13450888

申请日：2012-04-19

申请人： Chih-Ling Hung ,  Chien-Wen Chu ,  Hsin-Liang Chen ,  Wing-Chor Chan

发明人： Chih-Ling Hung ,  Chien-Wen Chu ,  Hsin-Liang Chen ,  Wing-Chor Chan

IPC分类号： H01L27/14 ,  H01L29/66 ,  H01L29/735 ,  H01L29/08 ,  H01L29/10

CPC分类号： H01L29/6625 ,  H01L29/0808 ,  H01L29/1008 ,  H01L29/404 ,  H01L29/735

摘要： A semiconductor structure includes a substrate, a first well having a first conductive type, a second well having a second conductive type, a body region, a first doped region, a second doped region, a third doped region and a field plate. The first and second wells are formed in the substrate. The body region is formed in the second well. The first and second doped regions are formed in the first well and the body region, respectively. The second and first doped regions have the same polarities, and the dopant concentration of the second doped region is higher than that of the first doped region. The third doped region is formed in the second well and located between the first and second doped regions. The third and first doped regions have reverse polarities. The field plate is formed on the surface region between the first and second doped regions.

摘要翻译： 半导体结构包括衬底，具有第一导电类型的第一阱，具有第二导电类型的第二阱，体区，第一掺杂区，第二掺杂区，第三掺杂区和场板。 在衬底中形成第一和第二阱。 身体区域形成在第二孔中。 第一和第二掺杂区分别形成在第一阱和体区中。 第二掺杂区域和第一掺杂区域具有相同的极性，并且第二掺杂区域的掺杂剂浓度高于第一掺杂区域的掺杂剂浓度。 第三掺杂区形成在第二阱中并位于第一和第二掺杂区之间。 第三和第一掺杂区域具有反向极性。 场板形成在第一和第二掺杂区域之间的表面区域上。

公开(公告)号：US20130277805A1

公开(公告)日：2013-10-24

申请号：US13450888

申请日：2012-04-19

申请人： Chih-Ling Hung ,  Chien-Wen Chu ,  Hsin-Liang Chen ,  Wing-Chor Chan

发明人： Chih-Ling Hung ,  Chien-Wen Chu ,  Hsin-Liang Chen ,  Wing-Chor Chan

IPC分类号： H01L29/73 ,  H01L21/331

CPC分类号： H01L29/6625 ,  H01L29/0808 ,  H01L29/1008 ,  H01L29/404 ,  H01L29/735

摘要： A semiconductor structure includes a substrate, a first well having a first conductive type, a second well having a second conductive type, a body region, a first doped region, a second doped region, a third doped region and a field plate. The first and second wells are formed in the substrate. The body region is formed in the second well. The first and second doped regions are formed in the first well and the body region, respectively. The second and first doped regions have the same polarities, and the dopant concentration of the second doped region is higher than that of the first doped region. The third doped region is formed in the second well and located between the first and second doped regions. The third and first doped regions have reverse polarities. The field plate is formed on the surface region between the first and second doped regions.

摘要翻译： 半导体结构包括衬底，具有第一导电类型的第一阱，具有第二导电类型的第二阱，体区，第一掺杂区，第二掺杂区，第三掺杂区和场板。 在衬底中形成第一和第二阱。 身体区域形成在第二孔中。 第一和第二掺杂区分别形成在第一阱和体区中。 第二掺杂区域和第一掺杂区域具有相同的极性，并且第二掺杂区域的掺杂剂浓度高于第一掺杂区域的掺杂剂浓度。 第三掺杂区形成在第二阱中并位于第一和第二掺杂区之间。 第三和第一掺杂区域具有反向极性。 场板形成在第一和第二掺杂区域之间的表面区域上。

公开(公告)号：US09029950B2

公开(公告)日：2015-05-12

申请号：US13425221

申请日：2012-03-20

申请人： Chien-Wen Chu ,  Wing-Chor Chan ,  Shyi-Yuan Wu

发明人： Chien-Wen Chu ,  Wing-Chor Chan ,  Shyi-Yuan Wu

IPC分类号： H01L21/84 ,  H01L27/12 ,  H01L29/78

CPC分类号： H01L29/7816

摘要： A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a substrate, a first source/drain region, a second source/drain region, a first stack structure and a second stack structure. The first source/drain region is formed in the substrate. The second source/drain region is formed in the substrate. The first stack structure is on the substrate between the first source/drain region and the second source/drain region. The first stack structure comprises a first dielectric layer and a first conductive layer on the first dielectric layer. The second stack structure is on the first stack structure. The second stack structure comprises a second dielectric layer and a second conductive layer on the second dielectric layer.

摘要翻译： 提供半导体结构及其形成方法。 半导体结构包括衬底，第一源极/漏极区域，第二源极/漏极区域，第一堆叠结构和第二堆叠结构。 第一源极/漏极区域形成在衬底中。 第二源极/漏极区域形成在衬底中。 第一堆叠结构在第一源极/漏极区域和第二源极/漏极区域之间的衬底上。 第一堆叠结构包括第一介电层和第一介电层上的第一导电层。 第二个堆栈结构是第一个堆叠结构。 第二堆叠结构包括第二电介质层和第二电介质层上的第二导电层。

公开(公告)号：US08669639B2

公开(公告)日：2014-03-11

申请号：US13493311

申请日：2012-06-11

申请人： Chih-Ling Hung ,  Chien-Wen Chu ,  Hsin-Liang Chen ,  Wing-Chor Chan

发明人： Chih-Ling Hung ,  Chien-Wen Chu ,  Hsin-Liang Chen ,  Wing-Chor Chan

IPC分类号： H01L29/735

CPC分类号： H01L21/8224 ,  H01L27/0259 ,  H01L27/082 ,  H01L29/402 ,  H01L29/735 ,  H01L29/861

摘要： A semiconductor element, a manufacturing method thereof and an operating method thereof are provided. The semiconductor element includes a substrate, a first well, a second well, a third well, a fourth well, a bottom layer, a first heavily doping region, a second heavily doping region, a third heavily doping region and a field plane. The first well, the bottom layer and the second well surround the third well for floating the third well and the substrate. The first, the second and the third heavily doping regions are disposed in the first, the second and the third wells respectively. The field plate is disposed above a junction between the first well and the fourth well.

摘要翻译： 提供半导体元件及其制造方法及其操作方法。 半导体元件包括衬底，第一阱，第二阱，第三阱，第四阱，底层，第一重掺杂区，第二重掺杂区，第三重掺杂区和场平面。 第一井，底层和第二井围绕第三井，用于浮置第三井和衬底。 第一，第二和第三重掺杂区域分别设置在第一，第二和第三阱中。 场板设置在第一井和第四井之间的连接点的上方。

公开(公告)号：US08610206B2

公开(公告)日：2013-12-17

申请号：US13030815

申请日：2011-02-18

申请人： Chien-Wen Chu ,  Wing-Chor Chan ,  Shyi-Yuan Wu

发明人： Chien-Wen Chu ,  Wing-Chor Chan ,  Shyi-Yuan Wu

IPC分类号： H01L29/78

CPC分类号： H01L29/7816 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/7835 ,  H01L29/7838

摘要： A semiconductor device comprises a source region, a drain region, and a drift region between the source and drain regions. A split gate is disposed over a portion of the drift region, and between the source and drain regions. The split gate includes first and second gate electrodes separated by a gate oxide layer. A self-aligned RESURF region is disposed within the drift region between the gate and the drain region. PI gate structures including an upper polysilicon layer are disposed near the drain region, such that the upper polysilicon layer can serve as a hard mask for the formation of the double RESURF structure, thereby allowing for self-alignment of the double RESURF structure.

摘要翻译： 半导体器件包括源极区域，漏极区域和源极区域与漏极区域之间的漂移区域。 分离栅极设置在漂移区域的一部分上，并且在源极和漏极区域之间。 分离栅极包括由栅极氧化物层隔开的第一和第二栅电极。 自对准RESURF区域设置在栅极和漏极区域之间的漂移区域内。 包括上多晶硅层的PI栅极结构设置在漏极区附近，使得上多晶硅层可以用作形成双RESURF结构的硬掩模，从而允许双RESURF结构的自对准。

公开(公告)号：US20130249007A1

公开(公告)日：2013-09-26

申请号：US13425221

申请日：2012-03-20

申请人： Chien-Wen Chu ,  Wing-Chor Chan ,  Shyi-Yuan Wu

发明人： Chien-Wen Chu ,  Wing-Chor Chan ,  Shyi-Yuan Wu

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L29/7816

摘要： A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a substrate, a first source/drain region, a second source/drain region, a first stack structure and a second stack structure. The first source/drain region is formed in the substrate. The second source/drain region is formed in the substrate. The first stack structure is on the substrate between the first source/drain region and the second source/drain region. The first stack structure comprises a first dielectric layer and a first conductive layer on the first dielectric layer. The second stack structure is on the first stack structure. The second stack structure comprises a second dielectric layer and a second conductive layer on the second dielectric layer.

摘要翻译： 提供半导体结构及其形成方法。 半导体结构包括衬底，第一源极/漏极区域，第二源极/漏极区域，第一堆叠结构和第二堆叠结构。 第一源极/漏极区域形成在衬底中。 第二源极/漏极区域形成在衬底中。 第一堆叠结构在第一源极/漏极区域和第二源极/漏极区域之间的衬底上。 第一堆叠结构包括第一介电层和第一介电层上的第一导电层。 第二个堆栈结构是第一个堆叠结构。 第二堆叠结构包括第二电介质层和第二电介质层上的第二导电层。

公开(公告)号：US20130328170A1

公开(公告)日：2013-12-12

申请号：US13493311

申请日：2012-06-11

申请人： Chih-Ling Hung ,  Chien-Wen Chu ,  Hsin-Liang Chen ,  Wing-Chor Chan

发明人： Chih-Ling Hung ,  Chien-Wen Chu ,  Hsin-Liang Chen ,  Wing-Chor Chan

IPC分类号： H01L27/082 ,  H01L21/8224

CPC分类号： H01L21/8224 ,  H01L27/0259 ,  H01L27/082 ,  H01L29/402 ,  H01L29/735 ,  H01L29/861

摘要： A semiconductor element, a manufacturing method thereof and an operating method thereof are provided. The semiconductor element includes a substrate, a first well, a second well, a third well, a fourth well, a bottom layer, a first heavily doping region, a second heavily doping region, a third heavily doping region and a field plane. The first well, the bottom layer and the second well surround the third well for floating the third well and the substrate. The first, the second and the third heavily doping regions are disposed in the first, the second and the third wells respectively. The field plate is disposed above a junction between the first well and the fourth well.

摘要翻译： 提供半导体元件及其制造方法及其操作方法。 半导体元件包括衬底，第一阱，第二阱，第三阱，第四阱，底层，第一重掺杂区，第二重掺杂区，第三重掺杂区和场平面。 第一井，底层和第二井围绕第三井，用于浮置第三井和衬底。 第一，第二和第三重掺杂区域分别设置在第一，第二和第三阱中。 场板设置在第一井和第四井之间的连接点的上方。