公开(公告)号：US20100244115A1

公开(公告)日：2010-09-30

申请号：US12814124

申请日：2010-06-11

申请人： Wlodek KURJANOWICZ ,  Steven SMITH

发明人： Wlodek KURJANOWICZ ,  Steven SMITH

IPC分类号： H01L29/78 ,  H01L21/768 ,  H01L21/336 ,  H01L23/525

CPC分类号： G11C17/16 ,  H01L23/5252 ,  H01L27/101 ,  H01L27/112 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

摘要： An anti-fuse memory cell having a variable thickness gate oxide. The variable thickness gate oxide has a thick gate oxide portion and a thin gate oxide portion, where the thing gate oxide portion has at least one dimension less than a minimum feature size of a process technology. The thin gate oxide can be rectangular in shape or triangular in shape. The anti-fuse transistor can be used in a two-transistor memory cell having an access transistor with a gate oxide substantially identical in thickness to the thick gate oxide of the variable thickness gate oxide of the anti-fuse transistor.

摘要翻译： 具有可变厚度栅极氧化物的反熔丝存储单元。 可变厚栅极氧化物具有厚的栅极氧化物部分和薄的栅极氧化物部分，其中栅极氧化物部分具有小于工艺技术的最小特征尺寸的至少一个尺寸。 薄栅氧化物的形状可以是矩形或三角形。 反熔丝晶体管可以用于具有存取晶体管的双晶体管存储单元，栅极氧化物的厚度与抗熔丝晶体管的可变厚栅极氧化物的厚栅极氧化物的厚度基本相同。

公开(公告)号：US20110312169A1

公开(公告)日：2011-12-22

申请号：US13219215

申请日：2011-08-26

申请人： Wlodek KURJANOWICZ ,  Steven SMITH

发明人： Wlodek KURJANOWICZ ,  Steven SMITH

IPC分类号： H01L21/336

CPC分类号： G11C17/16 ,  H01L23/5252 ,  H01L27/101 ,  H01L27/112 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

摘要： An anti-fuse memory cell having a variable thickness gate dielectric. The variable thickness dielectric has a thick portion and a thin portion, where the thin portion has at least one dimension less than a minimum feature size of a process technology. The thin portion can be rectangular in shape or triangular in shape. The anti-fuse transistor can be used in a two-transistor memory cell having an access transistor with a gate dielectric substantially identical in thickness to the thick portion of the variable thickness gate dielectric of the anti-fuse transistor.

摘要翻译： 具有可变厚度栅极电介质的反熔丝存储单元。 可变厚度电介质具有厚部分和薄部分，其中薄部分具有小于工艺技术的最小特征尺寸的至少一个尺寸。 薄部分的形状可以是矩形或三角形。 反熔丝晶体管可以用于具有存取晶体管的双晶体管存储单元，栅极电介质的厚度基本上与反熔丝晶体管的可变厚度栅极电介质的厚部相同。

公开(公告)号：US20070257331A1

公开(公告)日：2007-11-08

申请号：US11762552

申请日：2007-06-13

申请人： Wlodek KURJANOWICZ ,  Steven SMITH

发明人： Wlodek KURJANOWICZ ,  Steven SMITH

IPC分类号： H01L29/423 ,  H01L21/44

CPC分类号： G11C17/16 ,  H01L23/5252 ,  H01L27/101 ,  H01L27/112 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

摘要： An anti-fuse memory cell having a variable thickness gate oxide. The variable thickness gate oxide has a thick gate oxide portion and a thin gate oxide portion, where the thing gate oxide portion has at least one dimension less than a minimum feature size of a process technology. The thin gate oxide can be rectangular in shape or triangular in shape. The anti-fuse transistor can be used in a two-transistor memory cell having an access transistor with a gate oxide substantially identical in thickness to the thick gate oxide of the variable thickness gate oxide of the anti-fuse transistor.

摘要翻译： 具有可变厚度栅极氧化物的反熔丝存储单元。 可变厚栅极氧化物具有厚的栅极氧化物部分和薄的栅极氧化物部分，其中栅极氧化物部分具有小于工艺技术的最小特征尺寸的至少一个尺寸。 薄栅氧化物的形状可以是矩形或三角形。 反熔丝晶体管可以用于具有存取晶体管的双晶体管存储单元，栅极氧化物的厚度与抗熔丝晶体管的可变厚栅极氧化物的厚栅极氧化物的厚度基本相同。

公开(公告)号：US20120182782A1

公开(公告)日：2012-07-19

申请号：US13412500

申请日：2012-03-05

申请人： Wlodek KURJANOWICZ ,  Steven SMITH

发明人： Wlodek KURJANOWICZ ,  Steven SMITH

IPC分类号： G11C17/00

CPC分类号： G11C17/16 ,  G11C17/18 ,  G11C29/027 ,  H01L21/28211 ,  H01L23/5252 ,  H01L27/10 ,  H01L27/101 ,  H01L27/112 ,  H01L27/11206 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/42384 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods for testing unprogrammed single transistor and two transistor anti-fuse memory cells include testing for connections of the cells to a bitline by comparing a voltage characteristic of a bitline connected to the cell under test to a reference bitline having a predetermined voltage characteristic. Some methods can use test cells having an access transistor identically configured to the access transistor of a normal memory cell, but omitting the anti-fuse device found in the normal memory cell, for testing the presence of a connection of the normal memory cell to the bitline. Such a test cell can be used in a further test for determining the level of capacitive coupling of the wordline voltage to the bitlines relative to that of a normal memory cell under test.

摘要翻译： 用于测试未编程单晶体管和两晶体管反熔丝存储单元的方法包括通过将连接到被测电池的位线的电压特性与具有预定电压特性的参考位线进行比较来测试单元与位线的连接。 一些方法可以使用具有与正常存储器单元的存取晶体管相同配置的存取晶体管的测试单元，但是省略在正常存储单元中发现的反熔丝器件，用于测试正常存储器单元与 位线 这样的测试单元可用于进一步测试，用于确定字线电压与位线相对于正在测试的正常存储器单元的电容耦合水平。

公开(公告)号：US20100259965A1

公开(公告)日：2010-10-14

申请号：US12822332

申请日：2010-06-24

申请人： Wlodek KURJANOWICZ ,  Steven SMITH

发明人： Wlodek KURJANOWICZ ,  Steven SMITH

IPC分类号： G11C17/00

CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L21/28211 ,  H01L23/5252 ,  H01L27/10 ,  H01L27/101 ,  H01L27/112 ,  H01L27/11206 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/42384 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A high speed sensing scheme for a non-volatile memory array is disclosed. The memory array includes non volatile memory cells arranged in a complementary bitline configuration includes precharge circuits for precharging the bitlines to a first voltage level such as VSS, a reference circuits for applying a reference charge on the reference bitlines of the complementary bitline pairs, and bitline sense amplifiers for sensing a voltage differential between the complementary bitline pairs. A voltage on the data bitline being changed when a programmed non-volatile memory cell connected to an activated wordline couples the wordline voltage to the data bitline.

摘要翻译： 公开了一种用于非易失性存储器阵列的高速感测方案。 存储器阵列包括以互补位线配置布置的非易失性存储单元，包括用于将位线预充电到诸如VSS的第一电压电平的预充电电路，用于在补充位线对的参考位线上施加参考电荷的参考电路，以及位线 用于感测互补位线对之间的电压差的读出放大器。 当连接到激活的字线的编程的非易失性存储器单元将字线电压耦合到数据位线时，数据位线上的电压被改变。

公开(公告)号：US20090154217A1

公开(公告)日：2009-06-18

申请号：US12389933

申请日：2009-02-20

申请人： Wlodek KURJANOWICZ ,  Steven SMITH

发明人： Wlodek KURJANOWICZ ,  Steven SMITH

IPC分类号： G11C17/00 ,  G11C7/00 ,  G11C7/06 ,  G11C11/24

CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L21/28211 ,  H01L23/5252 ,  H01L27/10 ,  H01L27/101 ,  H01L27/112 ,  H01L27/11206 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/42384 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A high speed sensing scheme for a non-volatile memory array is disclosed. The memory array includes non volatile memory cells arranged in a complementary bitline configuration includes precharge circuits for precharging the bitlines to a first voltage level such as VSS, a reference circuits for applying a reference charge on the reference bitlines of the complementary bitline pairs, and bitline sense amplifiers for sensing a voltage differential between the complementary bitline pairs. A voltage on the data bitline being changed when a programmed non-volatile memory cell connected to an activated wordline couples the wordline voltage to the data bitline.

摘要翻译： 公开了一种用于非易失性存储器阵列的高速感测方案。 存储器阵列包括以互补位线配置布置的非易失性存储单元，包括用于将位线预充电到诸如VSS的第一电压电平的预充电电路，用于在补充位线对的参考位线上施加参考电荷的参考电路，以及位线 用于感测互补位线对之间的电压差的读出放大器。 当连接到激活的字线的编程的非易失性存储器单元将字线电压耦合到数据位线时，数据位线上的电压被改变。

公开(公告)号：US20070136514A1

公开(公告)日：2007-06-14

申请号：US11673703

申请日：2007-02-12

申请人： Alan ROTH ,  Sean LORD ,  Robert MCKENZIE ,  Dieter HAERLE ,  Steven SMITH

发明人： Alan ROTH ,  Sean LORD ,  Robert MCKENZIE ,  Dieter HAERLE ,  Steven SMITH

IPC分类号： G06F12/00

CPC分类号： G11C15/00

摘要： A priority encoder (PE) for a CAM, comprising a plurality of PE blocks, each receiving a plurality of match results corresponding to data entries in a corresponding data array block and, for determining an address of a highest priority data entry based on a physical location in the data array block during a CAM search-and-compare operation a register for storing a user defined priority value assigned to each PE block and means for evaluating priority values and the address determined by the plurality of PE blocks to select a PE block having the highest priority data entry.

摘要翻译： 一种用于CAM的优先编码器（PE），包括多个PE块，每个PE块都接收与对应的数据阵列块中的数据条目相对应的多个匹配结果，并且用于基于物理上的数据来确定最高优先级数据条目的地址 在CAM搜索与比较操作期间在数据阵列块中的位置存储用于分配给每个PE块的用户定义的优先级值的寄存器以及用于评估优先级值的装置和由多个PE块确定的地址以选择PE块 具有最高优先级的数据输入。