公开(公告)号：US20120194231A1

公开(公告)日：2012-08-02

申请号：US13442426

申请日：2012-04-09

申请人： Won Joo YUN ,  Hyun Woo LEE ,  Dong Suk SHIN

发明人： Won Joo YUN ,  Hyun Woo LEE ,  Dong Suk SHIN

IPC分类号： H03L7/08

CPC分类号： H03L7/0812

摘要： A method of controlling a power control circuit includes enabling a power cutoff signal when a delay locking operation of a Delay Locked Loop (DLL) circuit is completed, disabling the power cutoff signal for a predetermined time, and detecting a phase difference between a reference clock and a feedback clock to re-determine, on the basis of the detection result, whether or not to enable the power cutoff signal.

摘要翻译： 一种控制功率控制电路的方法包括：当延迟锁定环路（DLL）电路的延迟锁定操作完成时，使能电源切断信号，在预定时间内禁用电源切断信号，并检测参考时钟 以及反馈时钟，基于检测结果来重新确定是否启用电源切断信号。

公开(公告)号：US20120081161A1

公开(公告)日：2012-04-05

申请号：US12983177

申请日：2010-12-31

申请人： Dong Suk SHIN

发明人： Dong Suk SHIN

IPC分类号： H03L7/06

CPC分类号： G11C8/18 ,  G11C8/04 ,  H03L7/0812

摘要： A synchronization circuit includes a first loop circuit configured to set an initial delay time by using first initial delay information and generate a first delay signal by changing a delay time of a first input signal, a second loop circuit configured to set the initial delay time by using second initial delay information and generate a second delay signal by changing a delay time of a second input signal, a duty cycle correction unit configured to correct a duty cycle of the first delay signal by using the second delay signal, and an initial delay monitoring circuit configured to generate the first initial delay information and the second initial delay information in response to an internal delay signal of the first loop circuit and the first input signal.

摘要翻译： 同步电路包括第一环路电路，其被配置为通过使用第一初始延迟信息来设置初始延迟时间，并且通过改变第一输入信号的延迟时间来产生第一延迟信号，第二环路电路被配置为将初始延迟时间设置为 使用第二初始延迟信息并通过改变第二输入信号的延迟时间来产生第二延迟信号;占空比校正单元，被配置为通过使用第二延迟信号来校正第一延迟信号的占空比，以及初始延迟监视 电路，被配置为响应于第一环路电路和第一输入信号的内部延迟信号产生第一初始延迟信息和第二初始延迟信息。

公开(公告)号：US20120293225A1

公开(公告)日：2012-11-22

申请号：US13341436

申请日：2011-12-30

申请人： Dong Suk SHIN

发明人： Dong Suk SHIN

IPC分类号： H03K3/017

CPC分类号： H03K5/1565

摘要： A duty correction circuit includes a clock buffer configured to buffer an input clock and generate a buffer clock, a swing level conversion block configured to generate an internal clock, which transitions to levels of a sync voltage and a power supply voltage, in response to a voltage level of the buffer clock, a duty control block configured to generate duty information and frequency information by using a high pulse width and a low pulse width of the internal clock, and a current control block configured to control a time point, at which a logic value of the buffer clock transitions, in response to the duty information and the frequency information. The current control block includes a plurality of first current paths coupled in parallel to one another in order to control the time point at which the logic value of the buffer clock transitions.

摘要翻译： 一种占空比校正电路包括：时钟缓冲器，被配置为缓冲输入时钟并产生缓冲时钟;摆动电平转换模块，被配置为产生转换到同步电压和电源电压的电平的内部时钟，响应于 缓冲时钟的电压电平，配置为通过使用内部时钟的高脉冲宽度和低脉冲宽度来产生占空比信息和频率信息的占空比控制块，以及被配置为控制时间点的电流控制块， 响应于占空比信息和频率信息，缓冲时钟的逻辑值转换。 当前控制块包括彼此并联耦合的多个第一电流路径，以便控制缓冲时钟的逻辑值转变的时间点。

公开(公告)号：US20120194241A1

公开(公告)日：2012-08-02

申请号：US13219621

申请日：2011-08-27

申请人： Dong Suk SHIN

发明人： Dong Suk SHIN

IPC分类号： H03L7/06 ,  H03L7/00

CPC分类号： H03L7/0818 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/0816

摘要： A synchronization circuit includes a first delay unit configured to delay an input signal by a delay time corresponding to first initial delay information and generate a pre-delayed signal; a second delay unit configured to delay the pre-delayed signal by a delay time corresponding to second initial delay information and generate a delayed signal; and an initial delay monitoring circuit configured to generate the first initial delay information and the second initial delay information in response to internal delayed signals of the first delay unit and the input signal.

摘要翻译： 同步电路包括：第一延迟单元，被配置为将输入信号延迟与第一初始延迟信息相对应的延迟时间，并产生预延迟信号; 第二延迟单元，被配置为将预延迟信号延迟与第二初始延迟信息对应的延迟时间，并产生延迟信号; 以及初始延迟监视电路，被配置为响应于第一延迟单元和输入信号的内部延迟信号产生第一初始延迟信息和第二初始延迟信息。

公开(公告)号：US20130002323A1

公开(公告)日：2013-01-03

申请号：US13332964

申请日：2011-12-21

申请人： Dong Suk SHIN ,  Kwang Jin NA

发明人： Dong Suk SHIN ,  Kwang Jin NA

IPC分类号： H03K5/04

CPC分类号： H03K5/04

摘要： A duty cycle correction circuit includes a duty correction block configured to generate a first pre-corrected signal and a second pre-corrected signal in response to a duty code and an input signal; a duty-corrected signal generation block configured to generate a duty-corrected signal in response to a first select signal, a second select signal, the first pre-corrected signal and the second pre-corrected signal; and a control block configured to generate the duty code, the first select signal and the second select signal in response to the duty-corrected signal and the input signal.

摘要翻译： 占空比校正电路包括占空比校正块，其被配置为响应于占空比代码和输入信号产生第一预校正信号和第二预校正信号; 配置为响应于第一选择信号，第二选择信号，第一预校正信号和第二预校正信号产生占空比校正信号的占空比校正信号产生块; 以及控制块，被配置为响应于占空比校正信号和输入信号而产生占空比代码，第一选择信号和第二选择信号。