公开(公告)号：US20160163589A1

公开(公告)日：2016-06-09

申请号：US14955988

申请日：2015-12-01

申请人： Woo-Jin Lee ,  Byung-Hee Kim ,  Sang-Hoon Ahn ,  Woo-Kyung You ,  Jong-Min Baek ,  Nae-In Lee

发明人： Woo-Jin Lee ,  Byung-Hee Kim ,  Sang-Hoon Ahn ,  Woo-Kyung You ,  Jong-Min Baek ,  Nae-In Lee

IPC分类号： H01L21/768

CPC分类号： H01L21/76807 ,  H01L21/76816 ,  H01L21/76849 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2221/1047

摘要： A method of forming a semiconductor device can include forming an insulation layer using a material having a composition selected to provide resistance to subsequent etching process. The composition of the material can be changed to reduce the resistance of the material to the subsequent etching process at a predetermined level in the insulation layer. The subsequent etching process can be performed on the insulation layer to remove an upper portion of the insulation layer above the predetermined level and leave a lower portion of the insulation layer below the predetermined level between adjacent conductive patterns extending through the lower portion of the insulation layer. A low-k dielectric material can be formed on the lower portion of the insulation layer between the adjacent conductive patterns to replace the upper portion of the insulation layer above the predetermined level.

摘要翻译： 形成半导体器件的方法可以包括使用具有选择为提供对后续蚀刻工艺的电阻的组成的材料形成绝缘层。 可以改变材料的组成以将材料的电阻降低到绝缘层中预定水平的后续蚀刻工艺。 可以在绝缘层上执行随后的蚀刻工艺，以将绝缘层的上部去除在预定水平以上，并且将绝缘层的下部分留在延伸穿过绝缘层的下部的相邻导电图案之间的预定水平以下 。 可以在相邻导电图案之间的绝缘层的下部上形成低k介电材料，以将绝缘层的上部替换为高于预定水平。

公开(公告)号：US20160079115A1

公开(公告)日：2016-03-17

申请号：US14703556

申请日：2015-05-04

申请人： Kyoung-Woo Lee ,  Woo-Jin Lee ,  Jong-Sam Kim ,  Woo-Kyung You ,  Young-Sang Lee ,  Min Huh

发明人： Kyoung-Woo Lee ,  Woo-Jin Lee ,  Jong-Sam Kim ,  Woo-Kyung You ,  Young-Sang Lee ,  Min Huh

IPC分类号： H01L21/768

CPC分类号： H01L21/76802 ,  H01L21/31144 ,  H01L21/76804 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76814 ,  H01L21/76843 ,  H01L2221/1063

摘要： A method for fabricating a semiconductor device includes sequentially forming an interlayer insulating layer and a hard mask pattern including a first opening on a substrate including a lower pattern, forming a trench exposing the lower pattern in the interlayer insulating layer using the hard mask pattern, forming a liner layer including a first part formed along sidewalls and a bottom surface of the trench and a second part formed along a top surface of the hard mask pattern, forming a sacrificial pattern exposing the second part of the liner layer in the trench, removing the second part of the liner layer and the hard mask pattern using the sacrificial pattern, and after the removing of the hard mask pattern, removing the sacrificial pattern to expose the first part of the liner layer.

摘要翻译： 一种制造半导体器件的方法包括在包括下图案的衬底上顺序地形成层间绝缘层和包括第一开口的硬掩模图案，使用硬掩模图案形成在层间绝缘层中暴露下图案的沟槽，形成 包括沿着沟槽的侧壁和底表面形成的第一部分和沿着硬掩模图案的顶表面形成的第二部分的衬垫层，形成暴露沟槽中的衬垫层的第二部分的牺牲图案， 衬垫层的第二部分和使用牺牲图案的硬掩模图案，并且在去除硬掩模图案之后，去除牺牲图案以露出衬垫层的第一部分。

公开(公告)号：US09396988B2

公开(公告)日：2016-07-19

申请号：US14703556

申请日：2015-05-04

申请人： Kyoung-Woo Lee ,  Woo-Jin Lee ,  Jong-Sam Kim ,  Woo-Kyung You ,  Young-Sang Lee ,  Min Huh

发明人： Kyoung-Woo Lee ,  Woo-Jin Lee ,  Jong-Sam Kim ,  Woo-Kyung You ,  Young-Sang Lee ,  Min Huh

IPC分类号： H01L21/02 ,  H01L21/311 ,  H01L21/70 ,  H01L21/768

CPC分类号： H01L21/76802 ,  H01L21/31144 ,  H01L21/76804 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76814 ,  H01L21/76843 ,  H01L2221/1063

摘要： A method for fabricating a semiconductor device includes sequentially forming an interlayer insulating layer and a hard mask pattern including a first opening on a substrate including a lower pattern, forming a trench exposing the lower pattern in the interlayer insulating layer using the hard mask pattern, forming a liner layer including a first part formed along sidewalls and a bottom surface of the trench and a second part formed along a top surface of the hard mask pattern, forming a sacrificial pattern exposing the second part of the liner layer in the trench, removing the second part of the liner layer and the hard mask pattern using the sacrificial pattern, and after the removing of the hard mask pattern, removing the sacrificial pattern to expose the first part of the liner layer.

摘要翻译： 一种制造半导体器件的方法包括在包括下图案的衬底上顺序地形成层间绝缘层和包括第一开口的硬掩模图案，使用硬掩模图案形成在层间绝缘层中暴露下图案的沟槽，形成 包括沿着沟槽的侧壁和底表面形成的第一部分和沿着硬掩模图案的顶表面形成的第二部分的衬垫层，形成暴露沟槽中的衬垫层的第二部分的牺牲图案， 衬垫层的第二部分和使用牺牲图案的硬掩模图案，并且在去除硬掩模图案之后，去除牺牲图案以露出衬垫层的第一部分。