公开(公告)号：US08604586B2

公开(公告)日：2013-12-10

申请号：US12536819

申请日：2009-08-06

申请人： Wootag Kang ,  Jonghae Kim

发明人： Wootag Kang ,  Jonghae Kim

IPC分类号： H01L27/06

CPC分类号： H01L28/40 ,  H01L27/0805 ,  H01L27/101

摘要： Methods and devices related to a plurality of high breakdown voltage embedded capacitors are presented. A semiconductor device may include gate material embedded in an insulator, a plurality of metal contacts, and a plurality of capacitors. The plurality of capacitors may include a lower electrode, a dielectric formed so as to cover a surface of the lower electrode, and an upper electrode formed on the dielectric. Further, the plurality of contacts may connect each of the lower electrodes of the plurality of capacitors to the gate material. The plurality of capacitors may be connected in series via the gate material.

摘要翻译： 提出了与多个高击穿电压嵌入式电容器相关的方法和装置。 半导体器件可以包括嵌入绝缘体中的栅极材料，多个金属触点和多个电容器。 多个电容器可以包括下电极，形成为覆盖下电极的表面的电介质和形成在电介质上的上电极。 此外，多个触点可以将多个电容器中的每个下电极连接到栅极材料。 多个电容器可以经由栅极材料串联连接。

公开(公告)号：US20100237463A1

公开(公告)日：2010-09-23

申请号：US12405303

申请日：2009-03-17

申请人： Wootag Kang ,  Jonghae Kim ,  Jungwon Suh

发明人： Wootag Kang ,  Jonghae Kim ,  Jungwon Suh

IPC分类号： H01L27/08 ,  H01L21/02 ,  G06F17/50 ,  H01R43/00

CPC分类号： H01L27/0805 ,  G06F17/5068 ,  H01L28/40 ,  Y10T29/49117

摘要： Methods and devices of a capacitor in a semiconductor device having an increased capacitance are disclosed. In a particular embodiment, a method of forming a capacitor is disclosed. A section of a first insulating material between a first metal contact element and a second metal contact element is removed to form a channel. A second insulating material is deposited in the channel between the first metal contact element and the second metal contact element.

摘要翻译： 公开了具有增加的电容的半导体器件中的电容器的方法和装置。 在特定实施例中，公开了形成电容器的方法。 在第一金属接触元件和第二金属接触元件之间的第一绝缘材料的一部分被去除以形成通道。 在第一金属接触元件和第二金属接触元件之间的通道中沉积第二绝缘材料。

公开(公告)号：US20110031586A1

公开(公告)日：2011-02-10

申请号：US12536819

申请日：2009-08-06

申请人： Wootag Kang ,  Jonghae Kim

发明人： Wootag Kang ,  Jonghae Kim

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L28/40 ,  H01L27/0805 ,  H01L27/101

摘要： Methods and devices related to a plurality of high breakdown voltage embedded capacitors are presented. A semiconductor device may include gate material embedded in an insulator, a plurality of metal contacts, and a plurality of capacitors. The plurality of capacitors may include a lower electrode, a dielectric formed so as to cover a surface of the lower electrode, and an upper electrode formed on the dielectric. Further, the plurality of contacts may connect each of the lower electrodes of the plurality of capacitors to the gate material. The plurality of capacitors may be connected in series via the gate material.

摘要翻译： 提出了与多个高击穿电压嵌入式电容器相关的方法和装置。 半导体器件可以包括嵌入绝缘体中的栅极材料，多个金属触点和多个电容器。 多个电容器可以包括下电极，形成为覆盖下电极的表面的电介质和形成在电介质上的上电极。 此外，多个触点可以将多个电容器中的每个下电极连接到栅极材料。 多个电容器可以经由栅极材料串联连接。

公开(公告)号：US20110121372A1

公开(公告)日：2011-05-26

申请号：US12624509

申请日：2009-11-24

申请人： Wootag Kang ,  Zhongze Wang

发明人： Wootag Kang ,  Zhongze Wang

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/10894 ,  H01L27/10811 ,  H01L27/10897

摘要： A process for manufacturing an eDRAM device comprises fabricating semiconductor features on a semiconductor substrate, the semiconductor substrate including a DRAM area and logic area. The process also includes fabricating a first conductive layer in the DRAM area and in the logic area, the first conductive layer in communication with a first group of the semiconductor features. After fabricating the first conductive layer, a storage component is fabricated in communication with a second group of the semiconductor features within the DRAM area.

摘要翻译： 一种制造eDRAM器件的方法包括在半导体衬底上制造半导体器件，该半导体衬底包括一个DRAM区域和逻辑区域。 该工艺还包括在DRAM区域和逻辑区域中制造第一导电层，第一导电层与第一组半导体特征通信。 在制造第一导电层之后，制造与DRAM区域内的第二组半导体特征通信的存储部件。