-
公开(公告)号：US08258861B2
公开(公告)日：2012-09-04
申请号：US12684319
申请日：2010-01-08
申请人： Wreeju Bhaumik , Ashok Balivada , Senthil Gopalrao
发明人： Wreeju Bhaumik , Ashok Balivada , Senthil Gopalrao
IPC分类号： G05F1/10
CPC分类号： H03K19/0016 , G06F1/3203 , G06F1/3296 , H03L7/0805 , H03L7/0814 , H03L7/0816 , Y02D10/172
摘要： A system for reducing power consumption in a transistor-based system includes a measurement circuit and a comparator. The measurement circuit measures a delay of a transistor-based device and produces a control signal corresponding to the measured delay. The comparator compares the control signal to a predetermined threshold. Adjusting a power supply voltage of the transistor-based system based at least in part on a result of the comparison reduces the power consumed by the system.
摘要翻译： 用于降低基于晶体管的系统中的功耗的系统包括测量电路和比较器。 测量电路测量基于晶体管的器件的延迟并产生对应于测量的延迟的控制信号。 比较器将控制信号与预定阈值进行比较。 至少部分地基于比较的结果调整基于晶体管的系统的电源电压降低了系统消耗的功率。
-
公开(公告)号：US20110169563A1
公开(公告)日：2011-07-14
申请号：US12684319
申请日：2010-01-08
申请人： Wreeju Bhaumik , Ashok Balivada , Senthil Gopalrao
发明人： Wreeju Bhaumik , Ashok Balivada , Senthil Gopalrao
IPC分类号： G05F1/10
CPC分类号： H03K19/0016 , G06F1/3203 , G06F1/3296 , H03L7/0805 , H03L7/0814 , H03L7/0816 , Y02D10/172
摘要： A system for reducing power consumption in a transistor-based system includes a measurement circuit and a comparator. The measurement circuit measures a delay of a transistor-based device and produces a control signal corresponding to the measured delay. The comparator compares the control signal to a predetermined threshold. Adjusting a power supply voltage of the transistor-based system based at least in part on a result of the comparison reduces the power consumed by the system.
摘要翻译： 用于降低基于晶体管的系统中的功耗的系统包括测量电路和比较器。 测量电路测量基于晶体管的器件的延迟并产生对应于所测量的延迟的控制信号。 比较器将控制信号与预定阈值进行比较。 至少部分地基于比较的结果调整基于晶体管的系统的电源电压降低了系统消耗的功率。
-
公开(公告)号：US08994426B2
公开(公告)日：2015-03-31
申请号：US13600933
申请日：2012-08-31
CPC分类号： H03K3/017 , H03K7/08 , H03L7/08 , H03L7/0805 , H03L7/0814 , H03L7/0816
摘要： In various embodiments, systems and methods for generating high-precision pulse-width modulation include a delay-locked loop comprising multiple delay units having time-variable delays, control logic for selecting a subset S of the multiple delay units to thereby generate a time-invariant shift amount having a precision finer than that of a system clock and circuitry for applying the shift amount to rising and falling edges of a pulse-width modulation waveform to thereby generate a high-precision pulse-width modulation waveform.
摘要翻译： 在各种实施例中，用于产生高精度脉冲宽度调制的系统和方法包括包括具有时变延迟的多个延迟单元的延迟锁定环路，用于选择多个延迟单元的子集S的控制逻辑，从而产生时间 - 具有比用于将脉冲宽度调制波形的上升沿和下降沿施加移位量的系统时钟精度更高的精度的不变偏移量，从而生成高精度脉冲宽度调制波形。
-
公开(公告)号：US20140062551A1
公开(公告)日：2014-03-06
申请号：US13600933
申请日：2012-08-31
CPC分类号： H03K3/017 , H03K7/08 , H03L7/08 , H03L7/0805 , H03L7/0814 , H03L7/0816
摘要： In various embodiments, systems and methods for generating high-precision pulse-width modulation include a delay-locked loop comprising multiple delay units having time-variable delays, control logic for selecting a subset S of the multiple delay units to thereby generate a time-invariant shift amount having a precision finer than that of a system clock and circuitry for applying the shift amount to rising and falling edges of a pulse-width modulation waveform to thereby generate a high-precision pulse-width modulation waveform.
摘要翻译： 在各种实施例中，用于产生高精度脉冲宽度调制的系统和方法包括包括具有时变延迟的多个延迟单元的延迟锁定环路，用于选择多个延迟单元的子集S的控制逻辑，从而产生时间 - 具有比用于将脉冲宽度调制波形的上升沿和下降沿施加移位量的系统时钟精度更高的精度的不变偏移量，从而生成高精度脉冲宽度调制波形。
-
-
-
搜索结果
4 条记录 (耗时 0.014 秒)
