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    DYNAMICALLY ALLOCATED BUFFER POOLING
    2.
    发明申请
    DYNAMICALLY ALLOCATED BUFFER POOLING 有权

    公开(公告)号：US20230036531A1

    公开(公告)日：2023-02-02

    申请号：US17389272

    申请日：2021-07-29

    Applicant: XILINX, INC.

    Inventor： Krishnan SRINIVASAN ,  Shishir KUMAR ,  Sagheer AHMAD ,  Abbas MORSHED ,  Aman GUPTA

    IPC: G06F3/06

    Abstract: Some examples described herein provide a buffer memory pool circuitry that comprises a plurality of buffer memory circuits that store an entry identifier, a payload portion, and a next-entry pointer. The buffer memory pool circuitry further comprises a processor configured to identify an allocation request for a first virtual channel associated with a sequence of buffer memory circuits and comprising a start pointer identifying an initial buffer memory circuit. The processor is further configured to program the first virtual channel circuit based on setting the start pointer for the first virtual channel circuit to be equal to the entry identifier of the initial buffer memory circuit. The processor is also configured to monitor usage. A length of the sequence of buffer memory circuits of the first virtual channel circuit is defined by a start pointer for a second virtual channel circuit subsequent to the first virtual channel circuit.

    MULTI-USE CHIP-TO-CHIP INTERFACE
    4.
    发明公开
    MULTI-USE CHIP-TO-CHIP INTERFACE 审中-公开

    公开(公告)号：US20230141709A1

    公开(公告)日：2023-05-11

    申请号：US17551132

    申请日：2021-12-14

    Applicant: XILINX, INC.

    Inventor： Krishnan SRINIVASAN ,  Ygal ARBEL ,  Sagheer AHMAD

    IPC: G06F13/42

    CPC classification number: G06F13/4282 ,  G06F2213/0016

    Abstract: Systems, methods, and apparatuses are described that enable IC architectures to enable a single anchor to connect to and accept a variety of chiplets at any port by way of a programming model that enables the anchor or chiplet to dynamically adapt to configurations, requirements, or aspects of any coupled component and provide an interface for the coupled components.

    LOCALIZED NOC SWITCHING INTERCONNECT FOR HIGH BANDWIDTH INTERFACES
    5.
    发明申请
    LOCALIZED NOC SWITCHING INTERCONNECT FOR HIGH BANDWIDTH INTERFACES 有权

    公开(公告)号：US20220337923A1

    公开(公告)日：2022-10-20

    申请号：US17232207

    申请日：2021-04-16

    Applicant: XILINX, INC.

    Inventor： Aman GUPTA ,  Sagheer AHMAD ,  Ygal ARBEL ,  Abbas MORSHED ,  Eun Mi KIM

    IPC: H04Q3/00 ,  G06F13/40 ,  G06F13/16

    Abstract: Embodiments herein describe an integrated circuit that includes a NoC with at least two levels of switching: a sparse network and a non-blocking network. In one embodiment, the non-blocking network is a localized interconnect that provides an interface between the sparse network in the NoC and a memory system that requires additional bandwidth such as HBM2/3 or DDR5. Hardware elements connected to the NoC that do not need the additional benefits provided by the non-blocking network can connect solely to the sparse network. In this manner, the NoC provides a sparse network (which has a lower density of switching elements) for providing communication between lower bandwidth hardware elements and a localized non-blocking network for facilitating communication between the sparse network and higher bandwidth hardware elements.

    END-TO-END SAFETY MECHANISM FOR DISPLAY SYSTEM
    7.
    发明申请
    END-TO-END SAFETY MECHANISM FOR DISPLAY SYSTEM 有权

    公开(公告)号：US20250080716A1

    公开(公告)日：2025-03-06

    申请号：US18241161

    申请日：2023-08-31

    Applicant: XILINX, INC.

    Inventor： Yanran CHEN ,  Roger MAY ,  Sagheer AHMAD ,  Qingyi SHENG ,  Krishnan SRINIVASAN ,  Vishal SAGAR ,  Pramod BHARDWAJ ,  Yashu GOSAIN

    IPC: H04N17/00

    Abstract: Some examples described herein provide for display image data reliability and safety, for example end-to-end safety methods, apparatuses, and systems for display systems. One example includes a method, including replacing video frames from input video streams with a set of test frames. The method further includes generating an alpha-blended video stream based on the set of test frames and the input video streams. The method further includes generating and inserting cyclic redundancy check (CRC) information for the set of test frames into secondary data packets associated with the alpha-blended video stream. The method further includes processing the set of test frames and video frames by a display controller to generate an output video stream. The method further includes performing an error detection procedure for the set of test frames using the CRC information to detect an error associated with the set of video frames.

    METHODS TO EXTEND NOC INTERCONNECT ACROSS MULTIPLE DICE IN 3D
    8.
    发明申请
    METHODS TO EXTEND NOC INTERCONNECT ACROSS MULTIPLE DICE IN 3D 有权

    公开(公告)号：US20240403253A1

    公开(公告)日：2024-12-05

    申请号：US18204246

    申请日：2023-05-31

    Applicant: XILINX, INC.

    Inventor： Aman GUPTA ,  Krishnan SRINIVASAN ,  Brian C. GAIDE ,  Ahmad R. ANSARI ,  Sagheer AHMAD

    IPC: G06F13/40 ,  G06F13/42

    Abstract: Embodiments herein describe techniques to extend a network-on-chip (NoC) across multiple IC dice in 3D. An integrated circuit (IC) device includes first and second vertically-stacked IC dice, and an inter-die bus that interfaces between the second die and a NoC packet switch (NPS) of the first die. The inter-die bus may include one or more driver circuits coupled to inter-die links of the inter-die bus. Communications over the inter-die links may be synchronous (e.g., packet-based) or asynchronous with the NPS (e.g., based on a point-to-point protocol, such as an AXI protocol). The inter-die bus may interface with a circuit block of the second IC device via a point-to-point (e.g., AXI) protocol or via a NPS of the second IC die. The IC device may include multiple inter-die buses, which may expand inter-die and intra-die routing options

    ADAPTIVE ACCELERATION OF TRANSPORT LAYER SECURITY
    10.
    发明公开
    ADAPTIVE ACCELERATION OF TRANSPORT LAYER SECURITY 审中-公开

    公开(公告)号：US20230177146A1

    公开(公告)日：2023-06-08

    申请号：US17457839

    申请日：2021-12-06

    Applicant: XILINX, INC.

    Inventor： Jaideep DASTIDAR ,  Aman GUPTA ,  Krishnan SRINIVASAN ,  Sagheer AHMAD

    IPC: G06F21/54 ,  G06F21/85 ,  G06F21/62

    CPC classification number: G06F21/54 ,  G06F21/85 ,  G06F21/6209

    Abstract: Embodiments herein describe offloading encryption activities to a network interface controller/card (NIC) (e.g., a SmartNIC) which frees up server compute resources to focus on executing customer applications. In one embodiment, the smart NIC includes a system on a chip (SoC) implemented on an integrated circuit (IC) that includes an embedded processor. Instead of executing a transport layer security (TLS) stack entirely in the embedded processor, the embodiments herein offload certain TLS tasks to a Public Key Infrastructure (PKI) accelerator such as generating public-private key pairs.

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