公开(公告)号：US20240211422A1

公开(公告)日：2024-06-27

申请号：US18086531

申请日：2022-12-21

Applicant: XILINX, INC.

Inventor： Aman GUPTA ,  Krishnan SRINIVASAN ,  Ahmad R. ANSARI ,  Sagheer AHMAD

IPC: G06F13/40 ,  G06F12/1009

CPC classification number: G06F13/4022 ,  G06F12/1009 ,  G06F13/4036 ,  G06F13/4068 ,  G06F2213/0038

Abstract: Embodiments herein describe a multi-chip device that includes multiple ICs with interconnected NoCs. Embodiments herein provided address translation circuitry in the ICs. The address translation circuitry establish a hierarchy where traffic originating for a first IC that is intended for a destination on a second IC is first routed to the address translation circuitry on the second IC which then performs an address translation and inserts the traffic back on the NoC in the second IC but with a destination ID corresponding to the destination. In this manner, the IC can have additional address apertures only to route traffic to the address translation circuitry of the other ICs rather than having address apertures for every destination in the other ICs.

公开(公告)号：US20230308384A1

公开(公告)日：2023-09-28

申请号：US17705087

申请日：2022-03-25

Applicant: XILINX, INC.

Inventor： Aman GUPTA ,  Jaideep DASTIDAR ,  Jeffrey CUPPETT ,  Sagheer AHMAD

IPC: H04L49/109 ,  H04L45/24 ,  H04L45/74

CPC classification number: H04L45/24 ,  H04L45/74 ,  H04L49/109

Abstract: Methods and apparatus relating to transmission on physical channels, such as in networks on chips (NoCs) or between chiplets, are provided. One example apparatus generally includes a higher bandwidth client; a lower bandwidth client; a first destination; a second destination; and multiple physical channels coupled between the higher bandwidth client, the lower bandwidth client, the first destination, and the second destination, wherein the higher bandwidth client is configured to send first traffic, aggregated across the multiple physical channels, to the first destination and wherein the lower bandwidth client is configured to send second traffic, concurrently with sending the first traffic, from the lower bandwidth client, dispersed over two or more of the multiple physical channels, to the second destination.

公开(公告)号：US20230036531A1

公开(公告)日：2023-02-02

申请号：US17389272

申请日：2021-07-29

Applicant: XILINX, INC.

Inventor： Krishnan SRINIVASAN ,  Shishir KUMAR ,  Sagheer AHMAD ,  Abbas MORSHED ,  Aman GUPTA

IPC: G06F3/06

Abstract: Some examples described herein provide a buffer memory pool circuitry that comprises a plurality of buffer memory circuits that store an entry identifier, a payload portion, and a next-entry pointer. The buffer memory pool circuitry further comprises a processor configured to identify an allocation request for a first virtual channel associated with a sequence of buffer memory circuits and comprising a start pointer identifying an initial buffer memory circuit. The processor is further configured to program the first virtual channel circuit based on setting the start pointer for the first virtual channel circuit to be equal to the entry identifier of the initial buffer memory circuit. The processor is also configured to monitor usage. A length of the sequence of buffer memory circuits of the first virtual channel circuit is defined by a start pointer for a second virtual channel circuit subsequent to the first virtual channel circuit.

公开(公告)号：US20250007724A1

公开(公告)日：2025-01-02

申请号：US18215140

申请日：2023-06-27

Applicant: XILINX, INC.

Inventor： James ANDERSON ,  Aman GUPTA ,  James D. WESSELKAMPER

IPC: H04L9/32

Abstract: Techniques for network-on-chip (NoC) memory addressable encryption and authentication. In an embodiment, NoC circuitry includes NoC routing circuitry, memory circuitry that stores a security parameter, and security circuitry that secures (e.g., encrypts and/or authenticates) a payload based on the security parameter. The security circuitry may secure the payload before the payload is packetized for transmission through the NoC, after the payload is de-packetized for output to an endpoint, or as the payload transits the NoC. The security circuitry may be centralized or distributed amongst access points of the NoC. Distributed security circuitry may exchange a security parameter over a secure link of the NoC circuitry. The security circuitry may include decryption circuitry that decrypts a response from a first endpoint before the response is packetized for transmission through the NoC, after the response is de-packetized for output to a second endpoint, or as the response transits the NoC.

公开(公告)号：US20240387388A1

公开(公告)日：2024-11-21

申请号：US18199334

申请日：2023-05-18

Applicant: XILINX, INC.

Inventor： Brian C. GAIDE ,  Sagheer AHMAD ,  Aman GUPTA

IPC: H01L23/538 ,  H01L25/065 ,  H10B80/00

Abstract: Embodiments herein describe a memory controller (MC) in a first integrated circuit (IC) that connect to circuitry in the same integrated circuit (e.g., horizontal direction) and to circuitry in a second IC in the vertical direction. That is, the first and second ICs can be stacked on each other where the MC in the first IC provides an interface for both circuitry in the first IC as well as circuitry in the second IC to communicate with a separate memory device. Thus, the MC includes data paths in both the X direction (e.g., within the same IC) and the Y direction (e.g., to an external IC). In this manner, the MC can provide an interface for circuitry in multiple ICs (or dies or chiplets) to the same external memory device.

公开(公告)号：US20240403253A1

公开(公告)日：2024-12-05

申请号：US18204246

申请日：2023-05-31

Applicant: XILINX, INC.

Inventor： Aman GUPTA ,  Krishnan SRINIVASAN ,  Brian C. GAIDE ,  Ahmad R. ANSARI ,  Sagheer AHMAD

IPC: G06F13/40 ,  G06F13/42

Abstract: Embodiments herein describe techniques to extend a network-on-chip (NoC) across multiple IC dice in 3D. An integrated circuit (IC) device includes first and second vertically-stacked IC dice, and an inter-die bus that interfaces between the second die and a NoC packet switch (NPS) of the first die. The inter-die bus may include one or more driver circuits coupled to inter-die links of the inter-die bus. Communications over the inter-die links may be synchronous (e.g., packet-based) or asynchronous with the NPS (e.g., based on a point-to-point protocol, such as an AXI protocol). The inter-die bus may interface with a circuit block of the second IC device via a point-to-point (e.g., AXI) protocol or via a NPS of the second IC die. The IC device may include multiple inter-die buses, which may expand inter-die and intra-die routing options

公开(公告)号：US20240281537A1

公开(公告)日：2024-08-22

申请号：US18111808

申请日：2023-02-20

Applicant: XILINX, INC.

Inventor： Aman GUPTA ,  James D. WESSELKAMPER ,  James ANDERSON ,  Nader SHARIFI ,  Ahmad R. ANSARI ,  Sagheer AHMAD ,  Brian C. GAIDE

IPC: G06F21/57 ,  H04L9/06 ,  H04L9/08 ,  H04L9/14 ,  H04L9/30

CPC classification number: G06F21/575 ,  H04L9/0618 ,  H04L9/0822 ,  H04L9/0861 ,  H04L9/14 ,  H04L9/30 ,  G06F2221/034

Abstract: Some examples described herein provide for securely booting a heterogeneous integration circuitry apparatus. In an example, an apparatus (e.g., heterogeneous integration circuitry) includes a first portion and a second portion of one or more entropy sources on a first component and a second component, respectively. The apparatus also includes a key generation circuit communicatively coupled with the first portion and the second portion to generate a key encrypted key based on a first set of bits output by the first portion and a second set of bits output by the second portion. The apparatus also includes a key security circuit to generate, based on the key encrypted key and an encrypted public key stored at the apparatus, a plaintext public key to be used by a boot loader during a secure booting operation for the apparatus.

公开(公告)号：US20230177146A1

公开(公告)日：2023-06-08

申请号：US17457839

申请日：2021-12-06

Applicant: XILINX, INC.

Inventor： Jaideep DASTIDAR ,  Aman GUPTA ,  Krishnan SRINIVASAN ,  Sagheer AHMAD

IPC: G06F21/54 ,  G06F21/85 ,  G06F21/62

CPC classification number: G06F21/54 ,  G06F21/85 ,  G06F21/6209

Abstract: Embodiments herein describe offloading encryption activities to a network interface controller/card (NIC) (e.g., a SmartNIC) which frees up server compute resources to focus on executing customer applications. In one embodiment, the smart NIC includes a system on a chip (SoC) implemented on an integrated circuit (IC) that includes an embedded processor. Instead of executing a transport layer security (TLS) stack entirely in the embedded processor, the embodiments herein offload certain TLS tasks to a Public Key Infrastructure (PKI) accelerator such as generating public-private key pairs.

公开(公告)号：US20220337923A1

公开(公告)日：2022-10-20

申请号：US17232207

申请日：2021-04-16

Applicant: XILINX, INC.

Inventor： Aman GUPTA ,  Sagheer AHMAD ,  Ygal ARBEL ,  Abbas MORSHED ,  Eun Mi KIM

IPC: H04Q3/00 ,  G06F13/40 ,  G06F13/16

Abstract: Embodiments herein describe an integrated circuit that includes a NoC with at least two levels of switching: a sparse network and a non-blocking network. In one embodiment, the non-blocking network is a localized interconnect that provides an interface between the sparse network in the NoC and a memory system that requires additional bandwidth such as HBM2/3 or DDR5. Hardware elements connected to the NoC that do not need the additional benefits provided by the non-blocking network can connect solely to the sparse network. In this manner, the NoC provides a sparse network (which has a lower density of switching elements) for providing communication between lower bandwidth hardware elements and a localized non-blocking network for facilitating communication between the sparse network and higher bandwidth hardware elements.