公开(公告)号：US20230268280A1

公开(公告)日：2023-08-24

申请号：US17677899

申请日：2022-02-22

Applicant: XILINX, INC.

Inventor： Jaspreet Singh GANDHI ,  Brian C. GAIDE

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L23/5386 ,  H01L23/49822 ,  H01L24/06 ,  H01L23/49838 ,  H01L25/18 ,  H01L2224/0612

Abstract: A universal interposer for an integrated circuit (IC) device has a body having a first surface and a second surface opposite the first surface. A first region is formed on a first side of the body along a first edge. The first region has first slots, each having an identical first bond pad layout. A second region is formed on the first side along a second edge, opposite the first edge. The second region has second slots having an identical second bond pad layout. A third region having third slots is formed on the first side between the first and second regions, each slot having an identical third bond pad layout. A pad density of the third bond pad layout is greater than the first bond pad layout. One of the third slots is coupled to contact pads disposed in a region not directly below any of the second slots.

公开(公告)号：US20240203968A1

公开(公告)日：2024-06-20

申请号：US18081461

申请日：2022-12-14

Applicant: XILINX, INC.

Inventor： Jaspreet Singh GANDHI ,  Brian C. GAIDE

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L25/18 ,  H01L23/5381 ,  H01L24/08 ,  H01L24/16 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/08155 ,  H01L2224/16225 ,  H01L2224/81

Abstract: A chip package and method for fabricating the same are provided that include hybrid bonded bridge dies connecting IC dies on adjacent die stacks. In one example, a chip package includes an interconnect routing structure, a first die stack and a second die stack. The first die stack includes a top die disposed over a bottom die, the bottom die stacked on the interconnect routing structure. The second die stack also includes a top die disposed over a bottom die, the bottom die stacked on the interconnect routing structure. The first bridge die is electrically and mechanically coupled to the top dies of the first and second die stacks. The first bridge die having solid state circuitry that connects circuitries of the top dies of the first and second die stacks.

公开(公告)号：US20210249328A1

公开(公告)日：2021-08-12

申请号：US16786447

申请日：2020-02-10

Applicant: XILINX, INC.

Inventor： Gamal REFAI-AHMED ,  Suresh RAMALINGAM ,  Jaspreet Singh GANDHI ,  Cheang-Whang CHANG

IPC: H01L23/367 ,  H01L25/065

Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of electrically floating heat transfer structures for improved thermal management. In one example, a chip package assembly is provided. The chip package assembly includes a substrate, a first integrated circuit (IC) die and a plurality of electrically floating conductive heat transfer structures. The substrate has a first surface and an opposing second surface. The first IC die has a first surface, an opposing second surface, and four lateral sides. The second surface of the first IC die is mounted to the first surface of the substrate. The plurality of electrically floating conductive heat transfer structures extend in a first direction defined between the first and second surfaces of the first IC die. A first conductive heat transfer structure of the plurality of electrically floating conductive heat transfer structures are part of a first conductive heat transfer path having a length in the first direction at least as long as a distance between the first and second surfaces.

公开(公告)号：US20210366873A1

公开(公告)日：2021-11-25

申请号：US16880811

申请日：2020-05-21

Applicant: XILINX, INC.

Inventor： Jaspreet Singh GANDHI ,  Suresh RAMALINGAM ,  William E. ALLAIRE ,  Hong SHI ,  Kerry M. PIERCE

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A chip package assembly and method for fabricating the same are provided that provide a modular chip stack that can be matched with one or more chiplets. The use of chiplets enables the same modular stack to be utilized in a large number of different chip package assembly designs, resulting much faster development times at a fraction of the overall solution cost.

公开(公告)号：US20210134757A1

公开(公告)日：2021-05-06

申请号：US16672802

申请日：2019-11-04

Applicant: XILINX, INC.

Inventor： Jaspreet Singh GANDHI ,  Suresh RAMALINGAM

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/56

Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of posts in mold compound for improved resistance to delamination. In one example, a chip package assembly is provided that includes a first integrated circuit (IC) die, a substrate, a redistribution layer, a mold compound and a plurality of posts. The redistribution layer provides electrical connections between circuitry of the first IC die and circuitry of the substrate. The mold compound is disposed in contact with the first IC die and spaced from the substrate by the redistribution layer. The plurality of posts are disposed in the mold compound and are laterally spaced from the first IC die. The plurality of posts are not electrically connected to the circuitry of the first IC die.