公开(公告)号：US11923857B1

公开(公告)日：2024-03-05

申请号：US18102066

申请日：2023-01-26

Applicant: XILINX, INC.

Inventor： Hongtao Zhang ,  Ankur Jain ,  Yanfei Chen ,  Ronan Sean Casey ,  Winson Lin ,  Hsung Jai Im

IPC: H03L7/08 ,  H03L7/099 ,  H03M1/82

CPC classification number: H03L7/0802 ,  H03L7/0991 ,  H03M1/82

Abstract: Embodiments herein describe correcting nonlinearity in a Digital-to-Time Converter (DTC) by relaxing a DTC linearity requirement, which results in the correction being co-adapted with a DTC gain calibration loop which can operate in parallel with a DTC integral nonlinearity (INL) correction loop. In one embodiment, the DTC gain calibration loop and the DTC INL correction loop are constrained when determining a nonlinearity correction code to improve the likelihood they converge. Once determined, the nonlinearity correction code can be combined with an digital code output by a time-to-digital converter (TDC) to generate a phase difference between a reference clock and a feedback clock.

公开(公告)号：US11894959B2

公开(公告)日：2024-02-06

申请号：US17873002

申请日：2022-07-25

Applicant: XILINX, INC.

Inventor： Ronan Sean Casey ,  Lokesh Rajendran ,  Declan Carey ,  Kevin Zheng ,  Catherine Hearne ,  Hongtao Zhang

IPC: H04L25/49 ,  H04L27/04

CPC classification number: H04L25/4917 ,  H04L27/04

Abstract: Methods, systems, and apparatus described herein make a multi-level PAM signal (PAM-N signal) at a transmitter using CMOS-based components. By forming the PAM-N signal at the transmitter, receivers do not have to recombine and/or realign multiple signals and only employs a single transmission line channel (or two transmission line channels in differential implementations) to convey the data stream to the receiver from the transmitter.

公开(公告)号：US11489705B1

公开(公告)日：2022-11-01

申请号：US17019035

申请日：2020-09-11

Applicant: XILINX, INC.

Inventor： Ronan Sean Casey ,  Kevin Zheng ,  Catherine Hearne

IPC: H04L25/03 ,  H04L25/02 ,  H04L27/01

Abstract: Some examples described herein provide for an integrated circuit including a continuous time linear equalizer (CTLE) circuit and a method of operating the integrated circuit. In an example, an integrated circuit includes a transconductance amplifier stage and a transimpedance amplifier stage. The transconductance amplifier stage has a first input node and a first output node. The transconductance amplifier stage includes a first complementary device inverter. The transimpedance amplifier stage has a second input node and a second output node. The first output node is electrically connected to the second input node. The transimpedance amplifier stage includes a second complementary device inverter.