Circuit for and method of receiving signals in an integrated circuit device

    公开(公告)号:US10715358B1

    公开(公告)日:2020-07-14

    申请号:US16205020

    申请日:2018-11-29

    申请人: Xilinx, Inc.

    IPC分类号: H04L25/03

    摘要: A circuit for receiving signals in an integrated circuit device. The circuit comprises a first equalizer circuit having a first input for receiving a first input signal and generating an output signal at a first output; a second equalizer circuit having a second input for receiving the output signal generated at the first output of the first equalizer circuit and having a second output; and a control circuit having a control output coupled to the second output of the second equalizer circuit; wherein the control circuit provides an offset cancellation signal or a loopback signal to the second output of the second equalizer circuit. A method of receiving signals in an integrated circuit is also described.

    Method and apparatus for providing a differential output driver with a cross-coupled cell
    2.
    发明授权
    Method and apparatus for providing a differential output driver with a cross-coupled cell 有权
    用于提供具有交叉耦合单元的差分输出驱动器的方法和装置

    公开(公告)号:US09294091B1

    公开(公告)日:2016-03-22

    申请号:US14056895

    申请日:2013-10-17

    申请人: Xilinx, Inc.

    IPC分类号: H03K3/03 H03K19/003 H03K3/015

    摘要: An integrated circuit and method for providing a differential transmission line driver are disclosed. One embodiment of the differential transmission line driver comprises a current mode logic (CML) stage, and a cross-coupled n-channel enhancement type metal-oxide semiconductor field-effect transistor (NMOS) stage, wherein the cross-coupled NMOS stage provides a feedback current to the CML stage, where each output voltage of the differential transmission line driver is characterized by symmetrical rising and falling edges.

    摘要翻译: 公开了一种用于提供差分传输线驱动器的集成电路和方法。 差分传输线驱动器的一个实施例包括电流模式逻辑(CML)级和交叉耦合的n沟道增强型金属氧化物半导体场效应晶体管(NMOS)级,其中交叉耦合NMOS级提供 反馈电流到CML级,其中差分传输线驱动器的每个输出电压的特征在于对称的上升和下降沿。

    Asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) timing adjustment based on output statistics

    公开(公告)号:US11190199B1

    公开(公告)日:2021-11-30

    申请号:US17103652

    申请日:2020-11-24

    申请人: XILINX, INC.

    IPC分类号: H03M1/06 H03M1/46 H03M1/38

    摘要: Examples herein relate to electronic devices that include an asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) that implements timing adjustment based on output statistics. In an example, an electronic device includes an asynchronous SAR ADC, a statistics monitor, and an operation setting circuit. The asynchronous SAR ADC is configured to output output data. The statistics monitor is configured to capture samples at a bit position of the output data. The statistics monitor is further configured to generate an operational setting based on the captured samples. The operation setting circuit is configured to adjust an operating condition of the asynchronous SAR ADC based on the operational setting.

    System and method for decision feedback equalizers

    公开(公告)号:US10892918B1

    公开(公告)日:2021-01-12

    申请号:US16523966

    申请日:2019-07-26

    申请人: Xilinx, Inc.

    IPC分类号: H04L25/03

    摘要: A speculative decision feedback equalizer with split unroll multiplexers is provided. The speculative decision feedback equalizer splits an unroll multiplexer into two multiplexers. One split multiplexer provides a data path for the unroll selection signal, and the other split multiplexer provides a separate data path for the summer differential tap. In this way, the loading of an input stage of the summer circuit and the loading from the h1 unrolling loop are decoupled, allowing each split multiplexer to be configured according to a specific timing requirement along a respective data path. Thus, timing performance of the speculative decision feedback equalizer is improved.

    On-die receiver coupling capacitance testing

    公开(公告)号:US10862714B1

    公开(公告)日:2020-12-08

    申请号:US16670175

    申请日:2019-10-31

    申请人: XILINX, INC.

    摘要: A method for testing on-die capacitors is provided. The method comprises transmitting, during a first time period, a first modulated testing signal from a first transmitter port of a transmitter to a first receiver port of a receiver along a first path of a differential signal, the first receiver port connected to a first on-die capacitor in the receiver along the first path; driving, during the first time period, a constant voltage on a second transmitter port of the transmitter to a second receiver port of the receiver along a second path of the differential signal comprising a second on-die capacitor; and determining whether the first on-die capacitor is functional, based on the first modulated testing signal.

    CMOS analog circuits having a triode-based active load

    公开(公告)号:US10998307B1

    公开(公告)日:2021-05-04

    申请号:US16889533

    申请日:2020-06-01

    申请人: Xilinx, Inc.

    摘要: An analog signal buffer is disclosed. The analog signal buffer may include a transconductance cell and an active load. The active load may load the current from the transconductance cell with a PMOS transistor and an NMOS transistor and provide a feedback resistance. A transimpedance amplifier is disclosed. The transimpedance amplifier may include a first cell configured to receive a first signal and output a second signal and a second cell coupled to the first cell. The second cell may include an active feedback structure configured to couple an output of the second cell to an input of the second cell.

    Low-power decision threshold control for high-speed signaling

    公开(公告)号:US10193540B1

    公开(公告)日:2019-01-29

    申请号:US15410566

    申请日:2017-01-19

    申请人: Xilinx, Inc.

    IPC分类号: H03K7/02 H04L25/49 H03K5/125

    摘要: An apparatus and method and system therefor relates generally to decision threshold control. In such an apparatus, an ac-coupler circuit is configured as a high-pass circuit path for a first frequency range. A buffer amplifier circuit is coupled in parallel with the ac-coupler circuit. The buffer amplifier circuit is configured as a low-pass circuit path for a second frequency range. An offset injection circuit is coupled to both the ac-coupler circuit and the buffer amplifier circuit and configured to inject an offset.