公开(公告)号：US10454418B1

公开(公告)日：2019-10-22

申请号：US15432781

申请日：2017-02-14

Applicant: Xilinx, Inc.

Inventor： Ankur Jain ,  Jaeseo Lee ,  Richard W. Swanson

IPC: H03B1/00 ,  H03K3/03 ,  H03L7/099 ,  G05F1/46 ,  G05F1/575

Abstract: In an example, a voltage-controlled oscillator (VCO) includes: an oscillator having a supply input; and a voltage regulator, coupled to the supply input. The voltage regulator includes: a first transistor and a second transistor providing a first source-coupled transistor pair, and a third transistor and a fourth transistor providing a second source-coupled transistor pair; an active load coupled to drains of the first, second, third, and fourth transistors; a first current source coupled to sources of the first and second transistors, and a second current source coupled to sources of the third and fourth transistors; a fifth transistor having a source and a drain coupled to the source and the drain, respectively, of the first transistor; and a sixth transistor having a source and a drain coupled to the source and the drain, respectively, of the third transistor.

公开(公告)号：US09559704B1

公开(公告)日：2017-01-31

申请号：US14938741

申请日：2015-11-11

Applicant: Xilinx, Inc.

Inventor： Anna W. Wong ,  Ankur Jain ,  Richard W. Swanson

IPC: H03L7/08 ,  H03L7/197

CPC classification number: H03L7/1974 ,  H03L7/18

Abstract: In an example, operating a PLL circuit includes generating an error signal in response to comparison of a reference clock signal having a reference frequency and a feedback clock signal having a feedback frequency, generating a plurality of clock signals having an output frequency based on the error signal, and generating the feedback clock signal from the plurality of clock signals based on a first divider value and a control value derived from a second divider value. Operating the PLL circuit further includes multiplying each of a first integer value and a first fractional value by a power of two to generate a second integer value and a second fractional value, respectively, generating the second divider value using a sigma-delta modulator (SDM) based on the second integer value and the second fractional value, and dividing the second divider value by the power of two to generate the first divider value.

Abstract translation: 在一个示例中，操作PLL电路包括响应于具有参考频率的参考时钟信号和具有反馈频率的反馈时钟信号的比较来产生误差信号，产生具有基于误差的输出频率的多个时钟信号 信号，并且基于第一分频器值和从第二分频值导出的控制值从多个时钟信号产生反馈时钟信号。 操作PLL电路还包括将第一整数值和第一分数值中的每一个乘以2的幂来分别产生第二整数值和第二分数值，以使用Σ-Δ调制器（SDM）产生第二分频器值 ），并且将第二分频值除以二的幂来产生第一分频值。

公开(公告)号：US11923857B1

公开(公告)日：2024-03-05

申请号：US18102066

申请日：2023-01-26

Applicant: XILINX, INC.

Inventor： Hongtao Zhang ,  Ankur Jain ,  Yanfei Chen ,  Ronan Sean Casey ,  Winson Lin ,  Hsung Jai Im

IPC: H03L7/08 ,  H03L7/099 ,  H03M1/82

CPC classification number: H03L7/0802 ,  H03L7/0991 ,  H03M1/82

Abstract: Embodiments herein describe correcting nonlinearity in a Digital-to-Time Converter (DTC) by relaxing a DTC linearity requirement, which results in the correction being co-adapted with a DTC gain calibration loop which can operate in parallel with a DTC integral nonlinearity (INL) correction loop. In one embodiment, the DTC gain calibration loop and the DTC INL correction loop are constrained when determining a nonlinearity correction code to improve the likelihood they converge. Once determined, the nonlinearity correction code can be combined with an digital code output by a time-to-digital converter (TDC) to generate a phase difference between a reference clock and a feedback clock.

公开(公告)号：US10302504B1

公开(公告)日：2019-05-28

申请号：US15418544

申请日：2017-01-27

Applicant: Xilinx, Inc.

Inventor： Suresh P. Parameswaran ,  Boon Y. Ang ,  Ankur Jain

IPC: G01K7/01 ,  G01K7/16 ,  G01K15/00

Abstract: The disclosure provides simple, low-cost but accurate systems and related methods for on-die temperature sensing typically using calibration and without the need for precision voltage references. In some implementations, the system utilizes two user selectable temperature sensing elements and two user selectable DACs to provide a digital code for the sensed temperature. In some implementations, the two sensing elements can be used to calibrate against each other. For example, calibration can be useful to account for silicon local/global variation. Typically, one of the temperature sensors is diode-based, while the other is resistor-based. However, those of skill in the art will recognize that, in accordance with the disclosure, more than two sensors can be provided that can be calibrated against one another.

公开(公告)号：US11876523B1

公开(公告)日：2024-01-16

申请号：US18079649

申请日：2022-12-12

Applicant: XILINX, INC.

Inventor： Hongtao Zhang ,  Ankur Jain ,  Hsung Jai Im

IPC: H03L7/093 ,  H03L7/081 ,  G04F10/00 ,  H03M1/08 ,  H03L7/099

CPC classification number: H03L7/093 ,  G04F10/005 ,  H03L7/081 ,  H03L7/099 ,  H03M1/0854

Abstract: Embodiments herein describe normalizing an output of a TDC in a DPLL to a resolution of the TDC. A DTC can delay a reference clock which is then input into the TDC. The TDC outputs a digital code indicating a time difference between the delayed reference clock output by the DTC and a clock generated by a DCO in the DPLL. This digital code is normalized to a resolution of the TDC and the result is filtered by a DLF.