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1.发明申请公开(公告)号：US20110038087A1
公开(公告)日：2011-02-17
申请号：US12295467
申请日：2006-03-31
申请人： Xavier Moronval , Cedric Cassan , Jeffrey Jones , Olivier Lembeye
发明人： Xavier Moronval , Cedric Cassan , Jeffrey Jones , Olivier Lembeye
IPC分类号： H02H3/22
CPC分类号： H01L27/0248
摘要： A protection circuit apparatus comprises an electrostatic discharge circuit coupled to an isolation filter. The isolation filter comprises an inductor coupled to a ground-coupled capacitor, the inductor and the capacitor being coupled to the electrostatic discharge circuit. The inductor is also coupled to an electrostatic discharge sensitive device to be protected from an electrostatic discharge event.
摘要翻译： 保护电路装置包括耦合到隔离滤波器的静电放电电路。 隔离滤波器包括耦合到接地耦合电容器的电感器，电感器和电容器耦合到静电放电电路。 电感器还耦合到静电放电敏感器件以防止静电放电事件。
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2.发明授权公开(公告)号：US08369053B2
公开(公告)日：2013-02-05
申请号：US12295467
申请日：2006-03-31
申请人： Xavier Moronval , Cedric Cassan , Jeffrey Jones , Olivier Lembeye
发明人： Xavier Moronval , Cedric Cassan , Jeffrey Jones , Olivier Lembeye
IPC分类号： H02H9/00
CPC分类号： H01L27/0248
摘要： A protection circuit apparatus comprises an electrostatic discharge circuit coupled to an isolation filter. The isolation filter comprises an inductor coupled to a ground-coupled capacitor, the inductor and the capacitor being coupled to the electrostatic discharge circuit. The inductor is also coupled to an electrostatic discharge sensitive device to be protected from an electrostatic discharge event.
摘要翻译： 保护电路装置包括耦合到隔离滤波器的静电放电电路。 隔离滤波器包括耦合到接地耦合电容器的电感器，电感器和电容器耦合到静电放电电路。 电感器还耦合到静电放电敏感器件以防止静电放电事件。
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公开(公告)号：US08537512B2
公开(公告)日：2013-09-17
申请号：US12393166
申请日：2009-02-26
IPC分类号： H02H9/00
CPC分类号： H01L27/0255 , H01L29/0692 , H01L29/16 , H01L29/861
摘要： An electrostatic discharge (ESD) protection circuit (40) is coupled across input-output (I/O) pads (21) and common terminals (24) of a core circuit (22) to protect it from ESD events. The circuit (40) comprises, a unidirectional ESD clamp (23) and two or more floating diodes (42, 44) arranged in parallel opposed configuration in series with the ESD clamp (23), the combination coupled between the I/O pads (21) and the reference terminals (24). In a preferred arrangement, the two strings of opposed parallel coupled diodes (42, 44) are used with different numbers of diodes in each string. These diodes (42, 44) operate in forward conduction (43, 45), so the energy dissipated therein during an ESD event is much reduced compared to a reverse biased diode and they can have smaller area. Signal clipping at the I/O pad (21) is reduced, less power is dissipated and less chip area is utilized.
摘要翻译： 静电放电（ESD）保护电路（40）耦合在核心电路（22）的输入输出（I / O）焊盘（21）和公共端子（24）之间，以防止ESD事件。 电路（40）包括单向ESD钳位（23）和与ESD钳位（23）串联布置成平行相对构造的两个或更多个浮动二极管（42,44），该组合耦合在I / O焊盘 21）和参考端子（24）。 在优选的布置中，两串相对的并联耦合二极管（42,44）与每个串中使用不同数量的二极管。 这些二极管（42,44）在正向导通（43,45）中工作，因此与反向偏置二极管相比，在ESD事件期间消耗的能量大大降低，并且它们可以具有较小的面积。 I / O焊盘（21）上的信号削波减少，功率消耗减少，芯片面积减少。
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公开(公告)号：US10110178B2
公开(公告)日：2018-10-23
申请号：US14549756
申请日：2014-11-21
摘要： In a system comprising a plurality of gain elements configured in parallel to one another, a harmonically tuned filter provides an isolation circuit to prevent odd-mode differential oscillations. A harmonically tuned filter comprises resistors, inductors, and capacitors (RLC) to selectively allow one or more specific harmonics to pass through the isolation circuit to suppress the odd-mode oscillation. Direct current (DC) and other non-harmonically-related frequencies do not pass through the isolation circuit. Since the resistor is used to dissipate specifically the energy of the harmonic frequencies causing the odd-mode oscillation, the current density through the resistor is much lower than the current density of a typical odd-mode resistor without a harmonically tuned filter.
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5.发明申请FREQUENCY SELECTIVE ISOLATION CIRCUIT AND METHOD FOR SUPPRESSING PARAMETRIC OSCILLATION 审中-公开频率选择性隔离电路和抑制参数振荡的方法公开(公告)号：US20160056765A1
公开(公告)日：2016-02-25
申请号：US14549756
申请日：2014-11-21
CPC分类号： H03F3/211 , H01L23/66 , H01L2223/6611 , H01L2223/6644 , H01L2224/49175 , H03F1/32 , H03F3/195 , H03F2200/165 , H03F2200/451 , H03F2203/21106 , H03H7/09 , H03H2011/0488 , H03H2240/00
摘要： In a system comprising a plurality of gain elements configured in parallel to one another, a harmonically tuned filter provides an isolation circuit to prevent odd-mode differential oscillations. A harmonically tuned filter comprises resistors, inductors, and capacitors (RLC) to selectively allow one or more specific harmonics to pass through the isolation circuit to suppress the odd-mode oscillation. Direct current (DC) and other non-harmonically-related frequencies do not pass through the isolation circuit. Since the resistor is used to dissipate specifically the energy of the harmonic frequencies causing the odd-mode oscillation, the current density through the resistor is much lower than the current density of a typical odd-mode resistor without a harmonically tuned filter.
摘要翻译： 在包括彼此并联配置的多个增益元件的系统中，谐波调谐的滤波器提供隔离电路以防止奇数差分振荡。 谐波调谐滤波器包括电阻器，电感器和电容器（RLC），以选择性地允许一个或多个特定谐波通过隔离电路以抑制奇数振荡。 直流（DC）和其他非谐波相关频率不通过隔离电路。 由于电阻器用于特别耗散引起奇模振荡的谐波频率的能量，所以通过电阻器的电流密度比没有谐波调谐滤波器的典型奇模电阻器的电流密度要低得多。
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公开(公告)号：US20100214704A1
公开(公告)日：2010-08-26
申请号：US12393166
申请日：2009-02-26
CPC分类号： H01L27/0255 , H01L29/0692 , H01L29/16 , H01L29/861
摘要： An electrostatic discharge (ESD) protection circuit (40) is coupled across input-output (I/O) pads (21) and common terminals (24) of a core circuit (22) to protect it from ESD events. The circuit (40) comprises, a unidirectional ESD clamp (23) and two or more floating diodes (42, 44) arranged in parallel opposed configuration in series with the ESD clamp (23), the combination coupled between the I/O pads (21) and the reference terminals (24). In a preferred arrangement, the two strings of opposed parallel coupled diodes (42, 44) are used with different numbers of diodes in each string. These diodes (42, 44) operate in forward conduction (43, 45), so the energy dissipated therein during an ESD event is much reduced compared to a reverse biased diode and they can have smaller area. Signal clipping at the I/O pad (21) is reduced, less power is dissipated and less chip area is utilized.
摘要翻译： 静电放电（ESD）保护电路（40）耦合在核心电路（22）的输入输出（I / O）焊盘（21）和公共端子（24）之间，以防止ESD事件。 电路（40）包括单向ESD钳位（23）和与ESD钳位（23）串联布置成平行相对构造的两个或更多个浮动二极管（42,44），该组合耦合在I / O焊盘 21）和参考端子（24）。 在优选的布置中，两串相对的并联耦合二极管（42,44）与每个串中使用不同数量的二极管。 这些二极管（42,44）在正向导通（43,45）中工作，因此与反向偏置二极管相比，在ESD事件期间消耗的能量大大降低，并且它们可以具有较小的面积。 I / O焊盘（21）上的信号削波减少，功率消耗减少，芯片面积减少。
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