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1.发明申请Predictive Modeling of Interconnect Modules for Advanced On-Chip Interconnect Technology 失效用于高级片上互连技术的互连模块的预测建模公开(公告)号：US20090327983A1
公开(公告)日：2009-12-31
申请号：US12474297
申请日：2009-05-29
申请人： Xia Li , Wei Zhao , Yu Cao , Shiqun Gu , Seung H. Kang , Matthew Nowak
发明人： Xia Li , Wei Zhao , Yu Cao , Shiqun Gu , Seung H. Kang , Matthew Nowak
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A computer program product estimates performance of an interconnect structure of a semiconductor integrated circuit (IC). The program product includes code executing on a computer to calculate at least one electrical characteristic of the interconnect structure based on input data accounting for multiple layers of the interconnect structure. The electrical characteristics can be capacitance, resistance, and/or inductance. The capacitance may be based upon multiple components, including a fringe capacitance component, a terminal capacitance component, and a coupling capacitance component.
摘要翻译： 计算机程序产品估计半导体集成电路（IC）的互连结构的性能。 程序产品包括在计算机上执行的代码，用于基于考虑到互连结构的多层的输入数据来计算互连结构的至少一个电特性。 电气特性可以是电容，电阻和/或电感。 电容可以基于多个分量，包括边缘电容分量，端子电容分量和耦合电容分量。
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2.发明授权Predictive modeling of interconnect modules for advanced on-chip interconnect technology 失效用于先进片上互连技术的互连模块的预测建模公开(公告)号：US08429577B2
公开(公告)日：2013-04-23
申请号：US12474297
申请日：2009-05-29
申请人： Xia Li , Wei Zhao , Yu Cao , Shiqun Gu , Seung H. Kang , Matthew Nowak
发明人： Xia Li , Wei Zhao , Yu Cao , Shiqun Gu , Seung H. Kang , Matthew Nowak
CPC分类号： G06F17/5036
摘要： A computer program product estimates performance of an interconnect structure of a semiconductor integrated circuit (IC). The program product includes code executing on a computer to calculate at least one electrical characteristic of the interconnect structure based on input data accounting for multiple layers of the interconnect structure. The electrical characteristics can be capacitance, resistance, and/or inductance. The capacitance may be based upon multiple components, including a fringe capacitance component, a terminal capacitance component, and a coupling capacitance component.
摘要翻译： 计算机程序产品估计半导体集成电路（IC）的互连结构的性能。 程序产品包括在计算机上执行的代码，用于基于考虑到互连结构的多层的输入数据来计算互连结构的至少一个电特性。 电气特性可以是电容，电阻和/或电感。 电容可以基于多个分量，包括边缘电容分量，端子电容分量和耦合电容分量。
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3.发明申请PREDICTIVE MODELING OF CONTACT AND VIA MODULES FOR ADVANCED ON-CHIP INTERCONNECT TECHNOLOGY 失效联系方式的预测建模与先进的片上互连技术模块公开(公告)号：US20100057411A1
公开(公告)日：2010-03-04
申请号：US12493110
申请日：2009-06-26
申请人： Xia Li , Wei Zhao , David Bang , Yu Cao , Seung H. Kang , Matthew Nowak
发明人： Xia Li , Wei Zhao , David Bang , Yu Cao , Seung H. Kang , Matthew Nowak
CPC分类号： G06F17/5036
摘要： A computer program product estimates performance of a back end of line (BEOL) structure of a semiconductor integrated circuit (IC). Code executes on a computer to dynamically predict an electrical resistance of the BEOL structure based on input data specific to multiple layers of the BEOL structure. The BEOL structure can be a contact or a via. The layers of the contact/via include an inner filling material and an outer liner. The code accounts for a width scatter effect of the inner filling material, as well as a slope profile of the contact/via.
摘要翻译： 计算机程序产品估计半导体集成电路（IC）的后端（BEOL）结构的性能。 代码在计算机上执行，以基于特定于BEOL结构的多个层的输入数据来动态地预测BEOL结构的电阻。 BEOL结构可以是一个触点或通孔。 接触/通孔的层包括内部填充材料和外部衬垫。 该代码考虑了内部填充材料的宽度散射效应，以及接触/通孔的斜率分布。
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4.发明授权Predictive modeling of contact and via modules for advanced on-chip interconnect technology 失效用于高级片上互连技术的接触和通孔模块的预测建模公开(公告)号：US08483997B2
公开(公告)日：2013-07-09
申请号：US12493110
申请日：2009-06-26
申请人： Xia Li , Wei Zhao , David Bang , Yu Cao , Seung H. Kang , Matthew Nowak
发明人： Xia Li , Wei Zhao , David Bang , Yu Cao , Seung H. Kang , Matthew Nowak
IPC分类号： G06F7/60
CPC分类号： G06F17/5036
摘要： A computer program product estimates performance of a back end of line (BEOL) structure of a semiconductor integrated circuit (IC). Code executes on a computer to dynamically predict an electrical resistance of the BEOL structure based on input data specific to multiple layers of the BEOL structure. The BEOL structure can be a contact or a via. The layers of the contact/via include an inner filling material and an outer liner. The code accounts for a width scatter effect of the inner filling material, as well as a slope profile of the contact/via.
摘要翻译： 计算机程序产品估计半导体集成电路（IC）的后端（BEOL）结构的性能。 代码在计算机上执行，以基于特定于BEOL结构的多个层的输入数据来动态地预测BEOL结构的电阻。 BEOL结构可以是一个触点或通孔。 接触/通孔的层包括内部填充材料和外部衬垫。 该代码考虑了内部填充材料的宽度散射效应，以及接触/通孔的斜率分布。
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公开(公告)号：US08125040B2
公开(公告)日：2012-02-28
申请号：US12405461
申请日：2009-03-17
申请人： Seung H. Kang , Xia Li , Shiqun Gu , Matthew Nowak
发明人： Seung H. Kang , Xia Li , Shiqun Gu , Matthew Nowak
IPC分类号： H01L29/82
CPC分类号： H01L43/08 , G11C11/161 , H01L43/12
摘要： A method for forming a magnetic tunnel junction (MTJ) for magnetic random access memory (MRAM) using two masks includes depositing over an interlevel dielectric layer containing an exposed first interconnect metallization, a first electrode, a fixed magnetization layer, a tunneling barrier layer, a free magnetization layer and a second electrode. An MTJ structure including the tunnel barrier layer, free layer and second electrode is defined above the first interconnect metallization by a first mask. A first passivation layer encapsulates the MTJ structure, leaving the second electrode exposed. A third electrode is deposited in contact with the second electrode. A second mask is used to pattern a larger structure including the third electrode, the first passivation layer, the fixed magnetization layer and the first electrode. A second dielectric passivation layer covers the etched plurality of layers, the first interlevel dielectric layer and the first interconnect metallization.
摘要翻译： 使用两个掩模形成用于磁性随机存取存储器（MRAM）的磁性隧道结（MTJ）的方法包括在包含暴露的第一互连金属化的层间介质层上沉积，第一电极，固定磁化层，隧道势垒层， 自由磁化层和第二电极。 包括隧道势垒层，自由层和第二电极的MTJ结构通过第一掩模限定在第一互连金属化之上。 第一钝化层封装MTJ结构，留下第二电极。 沉积与第二电极接触的第三电极。 使用第二掩模来图案化包括第三电极，第一钝化层，固定磁化层和第一电极的较大结构。 第二电介质钝化层覆盖被蚀刻的多个层，第一层间介质层和第一互连金属化层。
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公开(公告)号：US20090261437A1
公开(公告)日：2009-10-22
申请号：US12405461
申请日：2009-03-17
申请人： Seung H. Kang , Xia Li , Shiqun Gu , Matthew Nowak
发明人： Seung H. Kang , Xia Li , Shiqun Gu , Matthew Nowak
CPC分类号： H01L43/08 , G11C11/161 , H01L43/12
摘要： A method for forming a magnetic tunnel junction (MTJ) for magnetic random access memory (MRAM) using two masks includes depositing over an interlevel dielectric layer containing an exposed first interconnect metallization, a first electrode, a fixed magnetization layer, a tunneling barrier layer, a free magnetization layer and a second electrode. An MTJ structure including the tunnel barrier layer, free layer and second electrode is defined above the first interconnect metallization by a first mask. A first passivation layer encapsulates the MTJ structure, leaving the second electrode exposed. A third electrode is deposited in contact with the second electrode. A second mask is used to pattern a larger structure including the third electrode, the first passivation layer, the fixed magnetization layer and the first electrode. A second dielectric passivation layer covers the etched plurality of layers, the first interlevel dielectric layer and the first interconnect metallization.
摘要翻译： 使用两个掩模形成用于磁性随机存取存储器（MRAM）的磁性隧道结（MTJ）的方法包括在包含暴露的第一互连金属化的层间介质层上沉积，第一电极，固定磁化层，隧道势垒层， 自由磁化层和第二电极。 包括隧道势垒层，自由层和第二电极的MTJ结构通过第一掩模限定在第一互连金属化之上。 第一钝化层封装MTJ结构，留下第二电极。 沉积与第二电极接触的第三电极。 使用第二掩模来图案化包括第三电极，第一钝化层，固定磁化层和第一电极的较大结构。 第二电介质钝化层覆盖被蚀刻的多个层，第一层间介质层和第一互连金属化层。
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7.发明申请Magnetic Tunnel Junction (MTJ) and Methods, and Magnetic Random Access Memory (MRAM) Employing Same 有权磁隧道结（MTJ）和方法，以及使用相同的磁性随机存取存储器（MRAM）公开(公告)号：US20100258887A1
公开(公告)日：2010-10-14
申请号：US12423298
申请日：2009-04-14
申请人： Xiaochun Zhu , Matthew Nowak , Xia Li , Seung H. Kang
发明人： Xiaochun Zhu , Matthew Nowak , Xia Li , Seung H. Kang
CPC分类号： H01L43/02 , G11C11/16 , G11C11/161 , G11C11/1659 , H01F10/3254 , H01F10/3272 , H01L27/228 , H01L43/08 , H01L43/12
摘要： Magnetic tunnel junctions (MTJs) and methods of forming same are disclosed. A pinned layer is disposed in the MTJ such that a free layer of the MTJ can couple to a drain of an access transistor when provided in a magnetic random access memory (MRAM) bitcell. This structure alters the write current flow direction to align the write current characteristics of the MTJ with write current supply capability of an MRAM bitcell employing the MTJ. As a result, more write current can be provided to switch the MTJ from a parallel (P) to anti-parallel (AP) state. An anti-ferromagnetic material (AFM) layer is provided on the pinned layer to fix pinned layer magnetization. To provide enough area for depositing the AFM layer to secure pinned layer magnetization, a pinned layer having a pinned layer surface area greater than a free layer surface area of the free layer is provided.
摘要翻译： 公开了磁隧道结（MTJ）及其形成方法。 被钉扎层设置在MTJ中，使得当提供在磁性随机存取存储器（MRAM）位单元中时，MTJ的自由层可以耦合到存取晶体管的漏极。 该结构改变写入电流流动方向，以使MTJ的写入电流特性与使用MTJ的MRAM位单元的写入电流供应能力对准。 结果，可以提供更多的写入电流以将MTJ从并行（P）切换到反并行（AP）状态。 在钉扎层上提供反铁磁材料（AFM）层以固定钉扎层的磁化强度。 为了提供足够的用于沉积AFM层以确保钉扎层磁化的区域，提供了具有大于自由层的自由层表面积的钉扎层表面积的钉扎层。
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公开(公告)号：US07829923B2
公开(公告)日：2010-11-09
申请号：US12256487
申请日：2008-10-23
申请人： Xia Li , Seung H. Kang , Xiaochun Zhu , Kangho Lee , Matthew Nowak
发明人： Xia Li , Seung H. Kang , Xiaochun Zhu , Kangho Lee , Matthew Nowak
IPC分类号： H01L27/108
摘要： In a particular embodiment, a method of forming a magnetic tunnel junction (MTJ) device includes applying a dielectric layer to a surface, applying a metal layer to the dielectric layer, and adding a cap layer on the dielectric layer. The method also includes forming a magnetic tunnel junction (MTJ) stack such that an electrode of the MTJ stack is disposed on the metal layer and the cap layer contacts a side portion of the metal layer. An adjustable depth to via may connect a top electrode of the MTJ stack to a top metal.
摘要翻译： 在特定实施例中，形成磁性隧道结（MTJ）器件的方法包括将电介质层施加到表面，向介电层施加金属层，以及在电介质层上添加覆盖层。 该方法还包括形成磁隧道结（MTJ）堆叠，使得MTJ堆叠的电极设置在金属层上，并且盖层接触金属层的侧部。 通孔的可调节深度可将MTJ叠层的顶部电极连接到顶部金属。
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公开(公告)号：US20100225435A1
公开(公告)日：2010-09-09
申请号：US12397488
申请日：2009-03-04
申请人： Xia Li , Matthew Nowak , Seung H. Kang , Brian Matthew Henderson
发明人： Xia Li , Matthew Nowak , Seung H. Kang , Brian Matthew Henderson
CPC分类号： H01F17/0006 , H01F41/046 , H01F41/14 , H01F2017/0053 , H01F2017/0066 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： An integrated magnetic film enhanced inductor and a method of forming an integrated magnetic film enhanced inductor are disclosed. The integrated magnetic film enhanced inductor includes an inductor metal having a first portion and a second portion, a top metal or bottom metal coupled to the inductor metal, and an isolation film disposed one of in, on, and adjacent to at least one of the first portion and the second portion of the inductor metal. The isolation film includes a magnetic material, such as a magnetic film.
摘要翻译： 公开了集成磁性膜增强型电感器和形成集成磁性膜增强型电感器的方法。 集成磁性膜增强电感器包括具有第一部分和第二部分的电感器金属，耦合到电感器金属的顶部金属或底部金属，以及设置在其中之一上，并且与其中的至少一个相邻的隔离膜 电感器金属的第一部分和第二部分。 隔离膜包括诸如磁性膜的磁性材料。
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公开(公告)号：US20100102404A1
公开(公告)日：2010-04-29
申请号：US12256487
申请日：2008-10-23
申请人： Xia Li , Seung H. Kang , Xiaochun Zhu , Kangho Lee , Matthew Nowak
发明人： Xia Li , Seung H. Kang , Xiaochun Zhu , Kangho Lee , Matthew Nowak
摘要： In a particular embodiment, a method of forming a magnetic tunnel junction (MTJ) device includes applying a dielectric layer to a surface, applying a metal layer to the dielectric layer, and adding a cap layer on the dielectric layer. The method also includes forming a magnetic tunnel junction (MTJ) stack such that an electrode of the MTJ stack is disposed on the metal layer and the cap layer contacts a side portion of the metal layer. An adjustable depth to via may connect a top electrode of the MTJ stack to a top metal.
摘要翻译： 在特定实施例中，形成磁性隧道结（MTJ）器件的方法包括将电介质层施加到表面，向介电层施加金属层，以及在电介质层上添加覆盖层。 该方法还包括形成磁隧道结（MTJ）堆叠，使得MTJ堆叠的电极设置在金属层上，并且盖层接触金属层的侧部。 通孔的可调节深度可将MTJ叠层的顶部电极连接到顶部金属。
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