公开(公告)号：US20060294347A1

公开(公告)日：2006-12-28

申请号：US11134687

申请日：2005-05-19

申请人： Xiang Zou ,  Hong Wang ,  Scott Rodgers ,  Darrell Boggs ,  Bryant Bigbee ,  Shivanandan Kaushik ,  Anil Aggarwal ,  Ittai Anati ,  Doron Orenstein ,  Per Hammarlund ,  John Shen ,  Larry Smith ,  James Crossland ,  Chris Newburn

发明人： Xiang Zou ,  Hong Wang ,  Scott Rodgers ,  Darrell Boggs ,  Bryant Bigbee ,  Shivanandan Kaushik ,  Anil Aggarwal ,  Ittai Anati ,  Doron Orenstein ,  Per Hammarlund ,  John Shen ,  Larry Smith ,  James Crossland ,  Chris Newburn

IPC分类号： G06F9/44

CPC分类号： G06F9/3851 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/4843 ,  G06F11/3409 ,  G06F11/348 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885

摘要： Method, apparatus, and system for a programmable event driven yield mechanism that may activate other threads. The yield mechanism may allow triggering of a service thread that may execute currently with a main thread upon occurrence of an architecturally-defined condition. The service thread may be activated, in response to the condition, with limited intervention of an operating system. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect an architecturally-defined condition. The apparatus may include an event handler to handle a yield event generated when the architecturally-defined condition has been detected. An architectural mechanism, including processor instructions and channel registers, may be utilized to allow user-level code to enable the yield event mechanism. Other embodiments are also described and claimed.

摘要翻译： 用于可激活其他线程的可编程事件驱动产量机制的方法，装置和系统。 收益机制可以允许在出现体系结构定义的条件时触发可以执行当前与主线程的服务线程。 响应于条件，可以在操作系统的有限干预下激活服务线程。 在一个实施例中，装置包括执行多个指令的执行资源和监视器以检测体系结构定义的条件。 该装置可以包括事件处理程序，用于处理当检测到体系结构定义的条件时产生的产出事件。 可以使用包括处理器指令和通道寄存器在内的架构机制来允许用户级代码来实现产出事件机制。 还描述和要求保护其他实施例。

公开(公告)号：US07366879B2

公开(公告)日：2008-04-29

申请号：US10951836

申请日：2004-09-27

申请人： Dion Rodgers ,  Darrell Boggs ,  Amit Merchant ,  Rajesh Kota ,  Rachel Hsu

发明人： Dion Rodgers ,  Darrell Boggs ,  Amit Merchant ,  Rajesh Kota ,  Rachel Hsu

IPC分类号： G06F9/30

CPC分类号： G06F9/30152 ,  G06F9/3808 ,  G06F9/382 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863

摘要： A method and apparatus are provided for entering and exiting multiple threads within a multithreaded processor. A state machine is maintained to indicate a respective status of an associated thread of multiple threads being executed within a multithreaded processor. A change of status for a first thread within the multithreaded processor is detected and, responsive to the change of status for the first thread within the multithreaded processor, a partitioning scheme for the functional unit is altered to service a second thread, but not the first thread, within the multithreaded processor when the change of the status of the first thread comprises a transition from an active state to an inactive state.

摘要翻译： 提供了用于在多线程处理器内进入和退出多个线程的方法和装置。 维护状态机以指示在多线程处理器内正在执行的多个线程的相关线程的相应状态。 检测多线程处理器内的第一线程的状态改变，并且响应于多线程处理器内的第一线程的状态改变，功能单元的分区方案被改变以服务于第二线程，但不是第一线程 线程，在多线程处理器内，当第一线程的状态改变包括从活动状态到非活动状态的转变时。

公开(公告)号：US07039794B2

公开(公告)日：2006-05-02

申请号：US10246887

申请日：2002-09-18

申请人： Dion Rodgers ,  Darrell Boggs ,  Amit Merchant ,  Rajesh Kota ,  Rachel Hsu ,  Keshavan Tiruvallur

发明人： Dion Rodgers ,  Darrell Boggs ,  Amit Merchant ,  Rajesh Kota ,  Rachel Hsu ,  Keshavan Tiruvallur

IPC分类号： G06F9/38

CPC分类号： G06F9/3851

摘要： A method includes detecting a first pending event related a first thread being processed within a multithreaded processor. Responsive to the detection of the first pending event, a second thread being processed within the multithreaded processor is monitored to detect an event handling point for the second thread. Responsive to the detection of the event handling point for the second thread, at least a first event handler is invoked to handle at least the first pending event.

摘要翻译： 一种方法包括检测与在多线程处理器内处理的第一线程有关的第一未决事件。 响应于检测到第一未决事件，监视在多线程处理器内处理的第二线程以检测第二线程的事件处理点。 响应于检测第二线程的事件处理点，至少调用第一事件处理程序来处理至少第一挂起事件。

公开(公告)号：US20060015707A1

公开(公告)日：2006-01-19

申请号：US10891165

申请日：2004-07-14

申请人： Gary Brown ,  Christopher Jones ,  Darrell Boggs

发明人： Gary Brown ,  Christopher Jones ,  Darrell Boggs

IPC分类号： G06F9/00

CPC分类号： G06F9/3017 ,  G06F9/26

摘要： A microprocessor including memory storage into which ISA customer code routines can be stored after having been decoded into their machine-native microinstructions. The customer code store is not subject to eviction and the like, as a cache memory would be. ISA level code can specify a routine for storage into the customer code store, at a time prior to its execution. The customer code store thus serves as a write-once execute-many library of pre-decoded routines which ISA level applications can subsequently use, permitting a system manufacturer to create a highly customized and optimized system.

摘要翻译： 包括存储器存储器的微处理器，ISA客户代码程序在被解码成其机器本机微指令之后可被存储到其中。 作为高速缓冲存储器，客户代码存储器不会被驱逐等等。 ISA级代码可以在执行之前指定一个用于存储到客户代码存储中的例程。 因此，客户代码存储库用作可以随后使用ISA级应用程序的预先解码的例程的一次写入的多执行程序库，允许系统制造商创建高度定制和优化的系统。

公开(公告)号：US20130297911A1

公开(公告)日：2013-11-07

申请号：US13463627

申请日：2012-05-03

申请人： Guillermo J. Rozas ,  Paul Serris ,  Brad Hoyt ,  Sridharan Ramakrishnan ,  Hens Vanderschoot ,  Ross Segelken ,  Darrell Boggs ,  Magnus Ekman

发明人： Guillermo J. Rozas ,  Paul Serris ,  Brad Hoyt ,  Sridharan Ramakrishnan ,  Hens Vanderschoot ,  Ross Segelken ,  Darrell Boggs ,  Magnus Ekman

IPC分类号： G06F9/30

CPC分类号： G06F9/3802 ,  G06F9/3814 ,  G06F9/3863

摘要： Embodiments related to re-dispatching an instruction selected for re-execution from a buffer upon a microprocessor re-entering a particular execution location after runahead are provided. In one example, a microprocessor is provided. The example microprocessor includes fetch logic, one or more execution mechanisms for executing a retrieved instruction provided by the fetch logic, and scheduler logic for scheduling the retrieved instruction for execution. The example scheduler logic includes a buffer for storing the retrieved instruction and one or more additional instructions, the scheduler logic being configured, upon the microprocessor re-entering at a particular execution location after runahead, to re-dispatch, from the buffer, an instruction that has been previously dispatched to one of the execution mechanisms.

摘要翻译： 在提供微控制器重新进入特定执行位置之后，重新分派从缓冲器重新执行的指令的实施例。 在一个示例中，提供微处理器。 示例微处理器包括提取逻辑，用于执行由提取逻辑提供的检索指令的一个或多个执行机制，以及用于调度所检索的指令以执行的调度器逻辑。 示例调度器逻辑包括用于存储检索到的指令和一个或多个附加指令的缓冲器，调度器逻辑被配置为在微控制器在经过前导头之后的特定执行位置重新进入时从缓冲器重新发送指令 以前已经分配到其中一个执行机制。

公开(公告)号：US20060218377A1

公开(公告)日：2006-09-28

申请号：US11090358

申请日：2005-03-24

申请人： Darrell Boggs ,  Chad Fogg ,  Christopher Jones ,  Gary Brown

发明人： Darrell Boggs ,  Chad Fogg ,  Christopher Jones ,  Gary Brown

IPC分类号： G06F9/30

CPC分类号： G06F9/30163 ,  G06F9/30167

摘要： A processor having an architecture including an instruction with a source operand from which the processor derives at least one of an operand value and a control value. The source operand may directly specify the operand value or the control value, with the other being implicitly specified. Or, both may be implicitly specified and derived from the source operand value. At least one of the operand value and the control value is implicit, not specified.

摘要翻译： 一种具有包括具有源操作数的指令的架构的处理器，所述处理器从所述源操作数导出操作数值和控制值中的至少一个。 源操作数可以直接指定操作数值或控制值，另一个被隐式指定。 或者，可以从源操作数值隐式指定和派生两者。 操作数值和控制值中的至少一个是隐式的，未指定。

公开(公告)号：US20050132376A1

公开(公告)日：2005-06-16

申请号：US11040773

申请日：2005-01-20

申请人： Dion Rodgers ,  Darrell Boggs ,  Amit Merchant ,  Rajesh Kota ,  Rachel Hsu ,  Keshavan Tiruvallur

发明人： Dion Rodgers ,  Darrell Boggs ,  Amit Merchant ,  Rajesh Kota ,  Rachel Hsu ,  Keshavan Tiruvallur

IPC分类号： G06F9/38 ,  G06F9/46

CPC分类号： G06F9/3851

摘要： A system includes a multithreaded processor, a memory to store the plurality of threads, and a bus to deliver the plurality of threads to the multithreaded processor. The multithreaded processor includes an event detector to detect a first event indication for a first thread. The event detector, responsive to the detection of the first event indication for the first thread, monitors a second thread being processed within the multithreaded processor to detect a clearing point for the second thread and, responsive to the detection of the clearing point for the second thread clears a functional unit within the multithreaded processor for at least the first thread.

摘要翻译： 系统包括多线程处理器，用于存储多个线程的存储器以及将多个线程传送到多线程处理器的总线。 多线程处理器包括事件检测器，用于检测第一线程的第一事件指示。 响应于对第一线程的第一事件指示的检测，事件检测器监视在多线程处理器内正在处理的第二线程以检测第二线程的清零点，并且响应于检测到第二线程的清除点 线程至少清除第一个线程的多线程处理器内的功能单元。

公开(公告)号：US06457119B1

公开(公告)日：2002-09-24

申请号：US09360192

申请日：1999-07-23

申请人： Darrell Boggs ,  Robert F. Krick ,  Chan Lee

发明人： Darrell Boggs ,  Robert F. Krick ,  Chan Lee

IPC分类号： G06F938

CPC分类号： G06F9/3865 ,  G06F9/3842 ,  G06F11/0721 ,  G06F11/0793 ,  G06F11/1405

摘要： Briefly, in accordance with one embodiment of the invention, a processor includes: a multiple unit instruction pipeline. An instruction pipeline includes a microcode source. The microcode source includes the capability of detecting the occurrence of at least one corrupted microcode instruction. The microcode source is also capable of signaling the occurrence of at least one corrupted microcode instruction to at least one other instruction pipeline unit. Briefly, in accordance with another embodiment of the invention, a method of executing microcode instructions includes the following. The existence of at least one corrupted microcode instruction is detected and the occurrence of at least one corrupted microcode instruction is signaled. Briefly, in accordance with one more embodiment of the invention, a system includes: a processor with a microcode source capable of detecting the occurrence of at least one corrupted microcode instruction and signaling the occurrence of at least one corrupted microcode instruction to at least one other instruction pipeline unit. The system employing the processor further includes main memory, a video card, a system bus, and bulk storage capability.

摘要翻译： 简而言之，根据本发明的一个实施例，处理器包括：多单元指令流水线。 指令流水线包括微码源。 微代码源包括检测至少一个损坏的微代码指令的发生的能力。 微代码源还能够向至少一个其他指令流水线单元发出至少一个损坏的微代码指令的发生。 简而言之，根据本发明的另一个实施例，执行微码指令的方法包括以下。 检测到存在至少一个损坏的微代码指令，并发出至少一个损坏的微代码指令的发生。 简而言之，根据本发明的另一实施例，一种系统包括：具有微码源的处理器，其能够检测至少一个损坏的微代码指令的发生，并向至少一个其他信号发送至少一个损坏的微代码指令的发生 指令流水线单元。 采用处理器的系统还包括主存储器，视频卡，系统总线和批量存储能力。

公开(公告)号：US09875105B2

公开(公告)日：2018-01-23

申请号：US13463627

申请日：2012-05-03

申请人： Guillermo J. Rozas ,  Paul Serris ,  Brad Hoyt ,  Sridharan Ramakrishnan ,  Hens Vanderschoot ,  Ross Segelken ,  Darrell Boggs ,  Magnus Ekman

发明人： Guillermo J. Rozas ,  Paul Serris ,  Brad Hoyt ,  Sridharan Ramakrishnan ,  Hens Vanderschoot ,  Ross Segelken ,  Darrell Boggs ,  Magnus Ekman

IPC分类号： G06F9/38

CPC分类号： G06F9/3802 ,  G06F9/3814 ,  G06F9/3863

摘要： Embodiments related to re-dispatching an instruction selected for re-execution from a buffer upon a microprocessor re-entering a particular execution location after runahead are provided. In one example, a microprocessor is provided. The example microprocessor includes fetch logic, one or more execution mechanisms for executing a retrieved instruction provided by the fetch logic, and scheduler logic for scheduling the retrieved instruction for execution. The example scheduler logic includes a buffer for storing the retrieved instruction and one or more additional instructions, the scheduler logic being configured, upon the microprocessor re-entering at a particular execution location after runahead, to re-dispatch, from the buffer, an instruction that has been previously dispatched to one of the execution mechanisms.

公开(公告)号：US20070083736A1

公开(公告)日：2007-04-12

申请号：US11244564

申请日：2005-10-06

申请人： Aravindh Baktha ,  KS Venkatraman ,  Darrell Boggs

发明人： Aravindh Baktha ,  KS Venkatraman ,  Darrell Boggs

IPC分类号： G06F9/40

CPC分类号： G06F9/3857 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3885

摘要： A digital signal processor which uses a RISC/CISC style front end and a VLIW style back end. Sequential ISA instructions are decoded into μops having a programmatic ordering. The μops are packed into a VLIW-like instruction packet according to a set of rules enforcing machine policy on e.g. data dependency, VLIW slot availability, maximum VLIW width, and so forth. Within the instruction packet, original program order is identified in case it is necessary to perform precise exception handling. The ISA code is executed as though it were on a RISC/CISC machine, but with VLIW style ILP efficiencies.

摘要翻译： 数字信号处理器，采用RISC / CISC风格的前端和VLIW风格的后端。 顺序ISA指令被解码成具有编程排序的muops。 根据一组执行机器策略的规则，将muops打包成类VLIW指令包。 数据依赖性，VLIW时隙可用性，最大VLIW宽度等。 在指令包中，在需要执行精确异常处理的情况下，识别原始程序顺序。 ISA代码就像在RISC / CISC机器上一样执行，但是具有VLIW风格的ILP效率。